📄 adc.lst
字号:
00000144 L_15:
81: ADC0Value[0] = ( AD0DR0 >> 6 ) & 0x3FF;
00000144 E5100000 LDR R0,=0xE0034010
00000148 E5901000 LDR R1,[R0,#0x0]
0000014C E1A01321 MOV R1,R1,LSR #6
00000150 E5100000 LDR R0,=0x3FF
00000154 E0011000 AND R1,R1,R0
00000158 E5100000 LDR R0,=ADC0Value ; ADC0Value
0000015C E5801000 STR R1,[R0,#0x0] ; ADC0Value
82: break;
00000160 EA000036 B L_14 ; Targ=0x240
83: case 0x02:
00000164 L_17:
84: ADC0Value[1] = ( AD0DR1 >> 6 ) & 0x3FF;
00000164 E5100000 LDR R0,=0xE0034014
00000168 E5901000 LDR R1,[R0,#0x0]
0000016C E1A01321 MOV R1,R1,LSR #6
00000170 E5100000 LDR R0,=0x3FF
00000174 E0011000 AND R1,R1,R0
00000178 E5100000 LDR R0,=ADC0Value + 0x4 ; ADC0Value+4
0000017C E5801000 STR R1,[R0,#0x0] ; ADC0Value+4
85: break;
00000180 EA00002E B L_14 ; Targ=0x240
86: case 0x04:
00000184 L_18:
87: ADC0Value[2] = ( AD0DR2 >> 6 ) & 0x3FF;
00000184 E5100000 LDR R0,=0xE0034018
00000188 E5901000 LDR R1,[R0,#0x0]
0000018C E1A01321 MOV R1,R1,LSR #6
00000190 E5100000 LDR R0,=0x3FF
00000194 E0011000 AND R1,R1,R0
00000198 E5100000 LDR R0,=ADC0Value + 0x8 ; ADC0Value+8
0000019C E5801000 STR R1,[R0,#0x0] ; ADC0Value+8
88: break;
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 10
000001A0 EA000026 B L_14 ; Targ=0x240
89: case 0x08:
000001A4 L_19:
90: ADC0Value[3] = ( AD0DR3 >> 6 ) & 0x3FF;
000001A4 E5100000 LDR R0,=0xE003401C
000001A8 E5901000 LDR R1,[R0,#0x0]
000001AC E1A01321 MOV R1,R1,LSR #6
000001B0 E5100000 LDR R0,=0x3FF
000001B4 E0011000 AND R1,R1,R0
000001B8 E5100000 LDR R0,=ADC0Value + 0xC ; ADC0Value+12
000001BC E5801000 STR R1,[R0,#0x0] ; ADC0Value+12
91: break;
000001C0 EA00001E B L_14 ; Targ=0x240
92: case 0x10:
000001C4 L_20:
93: ADC0Value[4] = ( AD0DR4 >> 6 ) & 0x3FF;
000001C4 E5100000 LDR R0,=0xE0034020
000001C8 E5901000 LDR R1,[R0,#0x0]
000001CC E1A01321 MOV R1,R1,LSR #6
000001D0 E5100000 LDR R0,=0x3FF
000001D4 E0011000 AND R1,R1,R0
000001D8 E5100000 LDR R0,=ADC0Value + 0x10 ; ADC0Value+16
000001DC E5801000 STR R1,[R0,#0x0] ; ADC0Value+16
94: break;
000001E0 EA000016 B L_14 ; Targ=0x240
95: case 0x20:
000001E4 L_21:
96: ADC0Value[5] = ( AD0DR5 >> 6 ) & 0x3FF;
000001E4 E5100000 LDR R0,=0xE0034024
000001E8 E5901000 LDR R1,[R0,#0x0]
000001EC E1A01321 MOV R1,R1,LSR #6
000001F0 E5100000 LDR R0,=0x3FF
000001F4 E0011000 AND R1,R1,R0
000001F8 E5100000 LDR R0,=ADC0Value + 0x14 ; ADC0Value+20
000001FC E5801000 STR R1,[R0,#0x0] ; ADC0Value+20
97: break;
00000200 EA00000E B L_14 ; Targ=0x240
98: case 0x40:
00000204 L_22:
99: ADC0Value[6] = ( AD0DR6 >> 6 ) & 0x3FF;
00000204 E5100000 LDR R0,=0xE0034028
00000208 E5901000 LDR R1,[R0,#0x0]
0000020C E1A01321 MOV R1,R1,LSR #6
00000210 E5100000 LDR R0,=0x3FF
00000214 E0011000 AND R1,R1,R0
00000218 E5100000 LDR R0,=ADC0Value + 0x18 ; ADC0Value+24
0000021C E5801000 STR R1,[R0,#0x0] ; ADC0Value+24
100: break;
00000220 EA000006 B L_14 ; Targ=0x240
101: case 0x80:
00000224 L_23:
102: ADC0Value[7] = ( AD0DR7 >> 6 ) & 0x3FF;
00000224 E5100000 LDR R0,=0xE003402C
00000228 E5901000 LDR R1,[R0,#0x0]
0000022C E1A01321 MOV R1,R1,LSR #6
00000230 E5100000 LDR R0,=0x3FF
00000234 E0011000 AND R1,R1,R0
00000238 E5100000 LDR R0,=ADC0Value + 0x1C ; ADC0Value+28
0000023C E5801000 STR R1,[R0,#0x0] ; ADC0Value+28
106: }
00000240 L_14:
107: AD0CR &= 0xF8FFFFFF; /* stop ADC now */
00000240 E5100000 LDR R0,=0xE0034000
00000244 E5901000 LDR R1,[R0,#0x0]
00000248 E3C11407 BIC R1,R1,#0x7000000
0000024C E5801000 STR R1,[R0,#0x0]
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 11
108: ADC0IntDone = 1;
00000250 E3A01001 MOV R1,#0x1
00000254 E5100000 LDR R0,=ADC0IntDone ; ADC0IntDone
00000258 E5801000 STR R1,[R0,#0x0] ; ADC0IntDone
109: }
0000025C L_13:
111: IDISABLE;
0000025C E8BD4000 LDMFD R13!,{LR}
00000260 E321F092 MSR CPSR_c,#0x92
00000264 E8BD4000 LDMFD R13!,{LR}
00000268 E16FF00E MSR SPSR_cxsf,R14
112: VICVectAddr = 0; /* Acknowledge Interrupt */
0000026C E3A01000 MOV R1,#0x0
00000270 E5100000 LDR R0,=0xFFFFF030
00000274 E5801000 STR R1,[R0,#0x0]
00000278 ; SCOPE-END
113: }
00000278 L_12:
00000278 E8BD4007 LDMIA R13!,{R0-R2,LR}
0000027C E25EF004 SUBS R15,R14,#0x0004
00000280 ENDP ; 'ADC0Handler?A'
*** CODE SEGMENT '?PR?ADC1Handler?A?adc':
124: void ADC1Handler (void) __irq
00000000 E92D4007 STMDB R13!,{R0-R2,LR}
125: {
00000004 ; SCOPE-START
128: IENABLE; /* handles nested interrupt */
00000004 E14FE000 MRS R14,SPSR
00000008 E92D4000 STMFD R13!,{LR}
0000000C E321F01F MSR CPSR_c,#0x1F
00000010 E92D4000 STMFD R13!,{LR}
130: regVal = AD1STAT; /* Read ADC will clear the interrupt */
00000014 E5100000 LDR R0,=0xE0060030
00000018 E5901000 LDR R1,[R0,#0x0]
0000001C ---- Variable 'regVal' assigned to Register 'R1' ----
131: if ( regVal & 0x0000FF00 ) /* check OVERRUN error first */
0000001C E1A00001 MOV R0,R1 ; regVal
00000020 E3100CFF TST R0,#0xFF00 ; regVal
00000024 0A000031 BEQ L_24 ; Targ=0xF0
133: regVal = (regVal & 0x0000FF00) >> 0x08;
00000028 E2011CFF AND R1,R1,#0xFF00 ; regVal
0000002C E1A01421 MOV R1,R1,LSR #8
136: switch ( regVal )
00000030 E1A00001 MOV R0,R1 ; regVal
00000034 E3500002 CMP R0,#0x0002 ; regVal
00000038 0A000010 BEQ L_28 ; Targ=0x80
0000003C E3500004 CMP R0,#0x0004 ; regVal
00000040 0A000011 BEQ L_29 ; Targ=0x8C
00000044 E3500008 CMP R0,#0x0008 ; regVal
00000048 0A000012 BEQ L_30 ; Targ=0x98
0000004C E3500010 CMP R0,#0x0010 ; regVal
00000050 0A000013 BEQ L_31 ; Targ=0xA4
00000054 E3500020 CMP R0,#0x0020 ; regVal
00000058 0A000014 BEQ L_32 ; Targ=0xB0
0000005C E3500040 CMP R0,#0x0040 ; regVal
00000060 0A000015 BEQ L_33 ; Targ=0xBC
00000064 E3500080 CMP R0,#0x0080 ; regVal
00000068 0A000016 BEQ L_34 ; Targ=0xC8
0000006C E3500001 CMP R0,#0x0001 ; regVal
00000070 1A000016 BNE L_25 ; Targ=0xD0
138: case 0x01:
00000074 L_26:
139: regVal = AD1DR0;
00000074 E5100000 LDR R0,=0xE0060010
00000078 E5901000 LDR R1,[R0,#0x0]
140: break;
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 12
0000007C EA000013 B L_25 ; Targ=0xD0
141: case 0x02:
00000080 L_28:
142: regVal = AD1DR1;
00000080 E5100000 LDR R0,=0xE0060014
00000084 E5901000 LDR R1,[R0,#0x0]
143: break;
00000088 EA000010 B L_25 ; Targ=0xD0
144: case 0x04:
0000008C L_29:
145: regVal = AD1DR2;
0000008C E5100000 LDR R0,=0xE0060018
00000090 E5901000 LDR R1,[R0,#0x0]
146: break;
00000094 EA00000D B L_25 ; Targ=0xD0
147: case 0x08:
00000098 L_30:
148: regVal = AD1DR3;
00000098 E5100000 LDR R0,=0xE006001C
0000009C E5901000 LDR R1,[R0,#0x0]
149: break;
000000A0 EA00000A B L_25 ; Targ=0xD0
150: case 0x10:
000000A4 L_31:
151: regVal = AD1DR4;
000000A4 E5100000 LDR R0,=0xE0060020
000000A8 E5901000 LDR R1,[R0,#0x0]
152: break;
000000AC EA000007 B L_25 ; Targ=0xD0
153: case 0x20:
000000B0 L_32:
154: regVal = AD1DR5;
000000B0 E5100000 LDR R0,=0xE0060024
000000B4 E5901000 LDR R1,[R0,#0x0]
155: break;
000000B8 EA000004 B L_25 ; Targ=0xD0
156: case 0x40:
000000BC L_33:
157: regVal = AD1DR6;
000000BC E5100000 LDR R0,=0xE0060028
000000C0 E5901000 LDR R1,[R0,#0x0]
158: break;
000000C4 EA000001 B L_25 ; Targ=0xD0
159: case 0x80:
000000C8 L_34:
160: regVal = AD1DR7;
000000C8 E5100000 LDR R0,=0xE006002C
000000CC E5901000 LDR R1,[R0,#0x0]
164: }
000000D0 L_25:
165: AD1CR &= 0xF8FFFFFF; /* stop ADC now */
000000D0 E5100000 LDR R0,=0xE0060000
000000D4 E5902000 LDR R2,[R0,#0x0]
000000D8 E3C22407 BIC R2,R2,#0x7000000
000000DC E5802000 STR R2,[R0,#0x0]
166: ADC1IntDone = 1;
000000E0 E3A02001 MOV R2,#0x1
000000E4 E5100000 LDR R0,=ADC1IntDone ; ADC1IntDone
000000E8 E5802000 STR R2,[R0,#0x0] ; ADC1IntDone
167: return;
000000EC EA000061 B L_35 ; Targ=0x278
168: }
000000F0 L_24:
170: if ( regVal & ADC_ADINT )
000000F0 E1A00001 MOV R0,R1 ; regVal
000000F4 E3100801 TST R0,#0x10000 ; regVal
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 13
000000F8 0A000057 BEQ L_36 ; Targ=0x25C
172: switch ( regVal & 0xFF ) /* check DONE bit */
000000FC E1A00001 MOV R0,R1 ; regVal
00000100 E20000FF AND R0,R0,#0x00FF ; regVal
00000104 E3500002 CMP R0,#0x0002
00000108 0A000015 BEQ L_40 ; Targ=0x164
0000010C E3500004 CMP R0,#0x0004
00000110 0A00001B BEQ L_41 ; Targ=0x184
00000114 E3500008 CMP R0,#0x0008
00000118 0A000021 BEQ L_42 ; Targ=0x1A4
0000011C E3500010 CMP R0,#0x0010
00000120 0A000027 BEQ L_43 ; Targ=0x1C4
00000124 E3500020 CMP R0,#0x0020
00000128 0A00002D BEQ L_44 ; Targ=0x1E4
0000012C E3500040 CMP R0,#0x0040
00000130 0A000033 BEQ L_45 ; Targ=0x204
00000134 E3500080 CMP R0,#0x0080
00000138 0A000039 BEQ L_46 ; Targ=0x224
0000013C E3500001 CMP R0,#0x0001
00000140 1A00003E BNE L_37 ; Targ=0x240
174: case 0x01:
00000144 L_38:
175: ADC1Value[0] = ( AD1DR0 >> 6 ) & 0x3FF;
00000144 E5100000 LDR R0,=0xE0060010
00000148 E5901000 LDR R1,[R0,#0x0]
0000014C E1A01321 MOV R1,R1,LSR #6
00000150 E5100000 LDR R0,=0x3FF
00000154 E0011000 AND R1,R1,R0
00000158 E5100000 LDR R0,=ADC1Value ; ADC1Value
0000015C E5801000 STR R1,[R0,#0x0] ; ADC1Value
176: break;
00000160 EA000036 B L_37 ; Targ=0x240
177: case 0x02:
00000164 L_40:
178: ADC1Value[1] = ( AD1DR1 >> 6 ) & 0x3FF;
00000164 E5100000 LDR R0,=0xE0060014
00000168 E5901000 LDR R1,[R0,#0x0]
0000016C E1A01321 MOV R1,R1,LSR #6
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