📄 adc.lst
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263 ** Function name: ADC0Read
264 **
265 ** Descriptions: Read ADC0 channel
266 **
267 ** parameters: Channel number
268 ** Returned value: Value read, if interrupt driven, return channel #
269 **
270 *****************************************************************************/
271 DWORD ADC0Read( BYTE channelNum )
272 {
273 1 #if !ADC_INTERRUPT_FLAG
DWORD regVal, ADC_Data;
#endif
276 1
277 1 /* channel number is 0 through 7 */
278 1 if ( channelNum >= ADC_NUM )
279 1 {
280 2 channelNum = 0; /* reset channel number to 0 */
281 2 }
282 1 AD0CR &= 0xFFFFFF00;
283 1 AD0CR |= (1 << 24) | (1 << channelNum);
284 1 /* switch channel,start A/D convert */
285 1 #if !ADC_INTERRUPT_FLAG
while ( 1 ) /* wait until end of A/D convert */
{
regVal = *(volatile unsigned long *)(AD0_BASE_ADDR
+ ADC_OFFSET + ADC_INDEX * channelNum);
/* read result of A/D conversion */
if ( regVal & ADC_DONE )
{
break;
}
}
AD0CR &= 0xF8FFFFFF; /* stop ADC now */
if ( regVal & ADC_OVERRUN ) /* save data when it's not overrun
otherwise, return zero */
{
return ( 0 );
}
ADC_Data = ( regVal >> 6 ) & 0x3FF;
return ( ADC_Data ); /* return A/D conversion value */
#else
306 1 return ( channelNum ); /* if it's interrupt driven, the
307 1 ADC reading is done inside the handler.
308 1 so, return channel number */
309 1 #endif
310 1 }
311
312 /*****************************************************************************
313 ** Function name: ADC1Read
314 **
315 ** Descriptions: Read ADC1 channel
316 **
317 ** parameters: Channel number
318 ** Returned value: Value read, if interrupt driven, return channel #
319 **
320 *****************************************************************************/
321 DWORD ADC1Read( BYTE channelNum )
322 {
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 6
323 1 #if !ADC_INTERRUPT_FLAG
DWORD regVal, ADC_Data;
#endif
326 1
327 1 /* channel number is 0 through 7 */
328 1 if ( channelNum >= ADC_NUM )
329 1 {
330 2 channelNum = 0; /* reset channel number to 0 */
331 2 }
332 1 AD1CR &= 0xFFFFFF00;
333 1 AD1CR |= (1 << 24) | (1 << channelNum);
334 1 /* switch channel,start A/D convert */
335 1 #if !ADC_INTERRUPT_FLAG
while ( 1 ) /* wait until end of A/D convert */
{
regVal = *(volatile unsigned long *)(AD1_BASE_ADDR
+ ADC_OFFSET + ADC_INDEX * channelNum);
/* read result of A/D conversion */
if ( regVal & ADC_DONE )
{
break;
}
}
AD1CR &= 0xF8FFFFFF; /* stop ADC now */
if ( regVal & ADC_OVERRUN ) /* save data when it's not overrun
otherwise, return zero */
{
return ( 0 );
}
ADC_Data = ( regVal >> 6 ) & 0x3FF;
return ( ADC_Data ); /* return A/D conversion value */
#else
357 1 return ( channelNum );
358 1 #endif
359 1 }
360
361 /*********************************************************************************
362 ** End Of File
363 *********************************************************************************/
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 7
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN CODE16 (install_irq?T)
EXTERN CODE16 (?C?UDIV?T)
*** PUBLICS:
PUBLIC ADC0Handler?A
PUBLIC ADC1Handler?A
PUBLIC ADCInit?T
PUBLIC ADC0Read?T
PUBLIC ADC1Read?T
PUBLIC ADC0Value
PUBLIC ADC1Value
PUBLIC ADC0IntDone
PUBLIC ADC1IntDone
*** DATA SEGMENT '?DT0?adc':
00000000 ADC0Value:
00000000 DS 32
00000020 ADC1Value:
00000020 DS 32
00000040 ADC0IntDone:
00000040 BEGIN_INIT
00000040 00000000 DD 0x0
00000044 END_INIT
00000044 ADC1IntDone:
00000044 BEGIN_INIT
00000044 00000000 DD 0x0
00000048 END_INIT
*** CODE SEGMENT '?PR?ADC0Handler?A?adc':
30: void ADC0Handler (void) __irq
00000000 E92D4007 STMDB R13!,{R0-R2,LR}
31: {
00000004 ; SCOPE-START
34: IENABLE; /* handles nested interrupt */
00000004 E14FE000 MRS R14,SPSR
00000008 E92D4000 STMFD R13!,{LR}
0000000C E321F01F MSR CPSR_c,#0x1F
00000010 E92D4000 STMFD R13!,{LR}
36: regVal = AD0STAT; /* Read ADC will clear the interrupt */
00000014 E5100000 LDR R0,=0xE0034030
00000018 E5901000 LDR R1,[R0,#0x0]
0000001C ---- Variable 'regVal' assigned to Register 'R1' ----
37: if ( regVal & 0x0000FF00 ) /* check OVERRUN error first */
0000001C E1A00001 MOV R0,R1 ; regVal
00000020 E3100CFF TST R0,#0xFF00 ; regVal
00000024 0A000031 BEQ L_1 ; Targ=0xF0
39: regVal = (regVal & 0x0000FF00) >> 0x08;
00000028 E2011CFF AND R1,R1,#0xFF00 ; regVal
0000002C E1A01421 MOV R1,R1,LSR #8
42: switch ( regVal )
00000030 E1A00001 MOV R0,R1 ; regVal
00000034 E3500002 CMP R0,#0x0002 ; regVal
00000038 0A000010 BEQ L_5 ; Targ=0x80
0000003C E3500004 CMP R0,#0x0004 ; regVal
00000040 0A000011 BEQ L_6 ; Targ=0x8C
00000044 E3500008 CMP R0,#0x0008 ; regVal
00000048 0A000012 BEQ L_7 ; Targ=0x98
0000004C E3500010 CMP R0,#0x0010 ; regVal
00000050 0A000013 BEQ L_8 ; Targ=0xA4
00000054 E3500020 CMP R0,#0x0020 ; regVal
00000058 0A000014 BEQ L_9 ; Targ=0xB0
0000005C E3500040 CMP R0,#0x0040 ; regVal
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 8
00000060 0A000015 BEQ L_10 ; Targ=0xBC
00000064 E3500080 CMP R0,#0x0080 ; regVal
00000068 0A000016 BEQ L_11 ; Targ=0xC8
0000006C E3500001 CMP R0,#0x0001 ; regVal
00000070 1A000016 BNE L_2 ; Targ=0xD0
44: case 0x01:
00000074 L_3:
45: regVal = AD0DR0;
00000074 E5100000 LDR R0,=0xE0034010
00000078 E5901000 LDR R1,[R0,#0x0]
46: break;
0000007C EA000013 B L_2 ; Targ=0xD0
47: case 0x02:
00000080 L_5:
48: regVal = AD0DR1;
00000080 E5100000 LDR R0,=0xE0034014
00000084 E5901000 LDR R1,[R0,#0x0]
49: break;
00000088 EA000010 B L_2 ; Targ=0xD0
50: case 0x04:
0000008C L_6:
51: regVal = AD0DR2;
0000008C E5100000 LDR R0,=0xE0034018
00000090 E5901000 LDR R1,[R0,#0x0]
52: break;
00000094 EA00000D B L_2 ; Targ=0xD0
53: case 0x08:
00000098 L_7:
54: regVal = AD0DR3;
00000098 E5100000 LDR R0,=0xE003401C
0000009C E5901000 LDR R1,[R0,#0x0]
55: break;
000000A0 EA00000A B L_2 ; Targ=0xD0
56: case 0x10:
000000A4 L_8:
57: regVal = AD0DR4;
000000A4 E5100000 LDR R0,=0xE0034020
000000A8 E5901000 LDR R1,[R0,#0x0]
58: break;
000000AC EA000007 B L_2 ; Targ=0xD0
59: case 0x20:
000000B0 L_9:
60: regVal = AD0DR5;
000000B0 E5100000 LDR R0,=0xE0034024
000000B4 E5901000 LDR R1,[R0,#0x0]
61: break;
000000B8 EA000004 B L_2 ; Targ=0xD0
62: case 0x40:
000000BC L_10:
63: regVal = AD0DR6;
000000BC E5100000 LDR R0,=0xE0034028
000000C0 E5901000 LDR R1,[R0,#0x0]
64: break;
000000C4 EA000001 B L_2 ; Targ=0xD0
65: case 0x80:
000000C8 L_11:
66: regVal = AD0DR7;
000000C8 E5100000 LDR R0,=0xE003402C
000000CC E5901000 LDR R1,[R0,#0x0]
70: }
000000D0 L_2:
71: AD0CR &= 0xF8FFFFFF; /* stop ADC now */
000000D0 E5100000 LDR R0,=0xE0034000
000000D4 E5902000 LDR R2,[R0,#0x0]
000000D8 E3C22407 BIC R2,R2,#0x7000000
000000DC E5802000 STR R2,[R0,#0x0]
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 9
72: ADC0IntDone = 1;
000000E0 E3A02001 MOV R2,#0x1
000000E4 E5100000 LDR R0,=ADC0IntDone ; ADC0IntDone
000000E8 E5802000 STR R2,[R0,#0x0] ; ADC0IntDone
73: return;
000000EC EA000061 B L_12 ; Targ=0x278
74: }
000000F0 L_1:
76: if ( regVal & ADC_ADINT )
000000F0 E1A00001 MOV R0,R1 ; regVal
000000F4 E3100801 TST R0,#0x10000 ; regVal
000000F8 0A000057 BEQ L_13 ; Targ=0x25C
78: switch ( regVal & 0xFF ) /* check DONE bit */
000000FC E1A00001 MOV R0,R1 ; regVal
00000100 E20000FF AND R0,R0,#0x00FF ; regVal
00000104 E3500002 CMP R0,#0x0002
00000108 0A000015 BEQ L_17 ; Targ=0x164
0000010C E3500004 CMP R0,#0x0004
00000110 0A00001B BEQ L_18 ; Targ=0x184
00000114 E3500008 CMP R0,#0x0008
00000118 0A000021 BEQ L_19 ; Targ=0x1A4
0000011C E3500010 CMP R0,#0x0010
00000120 0A000027 BEQ L_20 ; Targ=0x1C4
00000124 E3500020 CMP R0,#0x0020
00000128 0A00002D BEQ L_21 ; Targ=0x1E4
0000012C E3500040 CMP R0,#0x0040
00000130 0A000033 BEQ L_22 ; Targ=0x204
00000134 E3500080 CMP R0,#0x0080
00000138 0A000039 BEQ L_23 ; Targ=0x224
0000013C E3500001 CMP R0,#0x0001
00000140 1A00003E BNE L_14 ; Targ=0x240
80: case 0x01:
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