📄 adc.lst
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ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 1
ARM COMPILER V2.53, COMPILATION OF MODULE adc
OBJECT MODULE PLACED IN .\Obj\adc.obj
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe adc.c THUMB INCDIR(..\Common\inc) DEBUG PRINT(.\LST\ADC.LST) TABS(4) OBJECT(
-.\Obj\adc.obj)
stmt level source
1 /*****************************************************************************
2 * adc.c: ADC module file for Philips LPC214x Family Microprocessors
3 *
4 * Copyright(C) 2006, Philips Semiconductor
5 * All rights reserved.
6 *
7 * History
8 * 2005.10.01 ver 1.00 Prelimnary version, first Release
9 *
10 ******************************************************************************/
11 #include "LPC214x.h" /* LPC21xx definitions */
12 #include "type.h"
13 #include "irq.h"
14 #include "target.h"
15 #include "adc.h"
16
17 DWORD ADC0Value[ADC_NUM], ADC1Value[ADC_NUM];
18 DWORD ADC0IntDone = 0, ADC1IntDone = 0;
19
20 #if ADC_INTERRUPT_FLAG
21 /******************************************************************************
22 ** Function name: ADC0Handler
23 **
24 ** Descriptions: ADC0 interrupt handler
25 **
26 ** parameters: None
27 ** Returned value: None
28 **
29 ******************************************************************************/
30 void ADC0Handler (void) __irq
31 {
32 1 DWORD regVal;
33 1
34 1 IENABLE; /* handles nested interrupt */
35 1
36 1 regVal = AD0STAT; /* Read ADC will clear the interrupt */
37 1 if ( regVal & 0x0000FF00 ) /* check OVERRUN error first */
38 1 {
39 2 regVal = (regVal & 0x0000FF00) >> 0x08;
40 2 /* if overrun, just read ADDR to clear */
41 2 /* regVal variable has been reused. */
42 2 switch ( regVal )
43 2 {
44 3 case 0x01:
45 3 regVal = AD0DR0;
46 3 break;
47 3 case 0x02:
48 3 regVal = AD0DR1;
49 3 break;
50 3 case 0x04:
51 3 regVal = AD0DR2;
52 3 break;
53 3 case 0x08:
54 3 regVal = AD0DR3;
55 3 break;
56 3 case 0x10:
57 3 regVal = AD0DR4;
58 3 break;
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 2
59 3 case 0x20:
60 3 regVal = AD0DR5;
61 3 break;
62 3 case 0x40:
63 3 regVal = AD0DR6;
64 3 break;
65 3 case 0x80:
66 3 regVal = AD0DR7;
67 3 break;
68 3 default:
69 3 break;
70 3 }
71 2 AD0CR &= 0xF8FFFFFF; /* stop ADC now */
72 2 ADC0IntDone = 1;
73 2 return;
74 2 }
75 1
76 1 if ( regVal & ADC_ADINT )
77 1 {
78 2 switch ( regVal & 0xFF ) /* check DONE bit */
79 2 {
80 3 case 0x01:
81 3 ADC0Value[0] = ( AD0DR0 >> 6 ) & 0x3FF;
82 3 break;
83 3 case 0x02:
84 3 ADC0Value[1] = ( AD0DR1 >> 6 ) & 0x3FF;
85 3 break;
86 3 case 0x04:
87 3 ADC0Value[2] = ( AD0DR2 >> 6 ) & 0x3FF;
88 3 break;
89 3 case 0x08:
90 3 ADC0Value[3] = ( AD0DR3 >> 6 ) & 0x3FF;
91 3 break;
92 3 case 0x10:
93 3 ADC0Value[4] = ( AD0DR4 >> 6 ) & 0x3FF;
94 3 break;
95 3 case 0x20:
96 3 ADC0Value[5] = ( AD0DR5 >> 6 ) & 0x3FF;
97 3 break;
98 3 case 0x40:
99 3 ADC0Value[6] = ( AD0DR6 >> 6 ) & 0x3FF;
100 3 break;
101 3 case 0x80:
102 3 ADC0Value[7] = ( AD0DR7 >> 6 ) & 0x3FF;
103 3 break;
104 3 default:
105 3 break;
106 3 }
107 2 AD0CR &= 0xF8FFFFFF; /* stop ADC now */
108 2 ADC0IntDone = 1;
109 2 }
110 1
111 1 IDISABLE;
112 1 VICVectAddr = 0; /* Acknowledge Interrupt */
113 1 }
114
115 /******************************************************************************
116 ** Function name: ADC1Handler
117 **
118 ** Descriptions: ADC1 interrupt handler
119 **
120 ** parameters: None
121 ** Returned value: None
122 **
123 ******************************************************************************/
124 void ADC1Handler (void) __irq
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 3
125 {
126 1 DWORD regVal;
127 1
128 1 IENABLE; /* handles nested interrupt */
129 1
130 1 regVal = AD1STAT; /* Read ADC will clear the interrupt */
131 1 if ( regVal & 0x0000FF00 ) /* check OVERRUN error first */
132 1 {
133 2 regVal = (regVal & 0x0000FF00) >> 0x08;
134 2 /* if overrun, just read AD1DRx to clear */
135 2 /* regVal variable has been reused. */
136 2 switch ( regVal )
137 2 {
138 3 case 0x01:
139 3 regVal = AD1DR0;
140 3 break;
141 3 case 0x02:
142 3 regVal = AD1DR1;
143 3 break;
144 3 case 0x04:
145 3 regVal = AD1DR2;
146 3 break;
147 3 case 0x08:
148 3 regVal = AD1DR3;
149 3 break;
150 3 case 0x10:
151 3 regVal = AD1DR4;
152 3 break;
153 3 case 0x20:
154 3 regVal = AD1DR5;
155 3 break;
156 3 case 0x40:
157 3 regVal = AD1DR6;
158 3 break;
159 3 case 0x80:
160 3 regVal = AD1DR7;
161 3 break;
162 3 default:
163 3 break;
164 3 }
165 2 AD1CR &= 0xF8FFFFFF; /* stop ADC now */
166 2 ADC1IntDone = 1;
167 2 return;
168 2 }
169 1
170 1 if ( regVal & ADC_ADINT )
171 1 {
172 2 switch ( regVal & 0xFF ) /* check DONE bit */
173 2 {
174 3 case 0x01:
175 3 ADC1Value[0] = ( AD1DR0 >> 6 ) & 0x3FF;
176 3 break;
177 3 case 0x02:
178 3 ADC1Value[1] = ( AD1DR1 >> 6 ) & 0x3FF;
179 3 break;
180 3 case 0x04:
181 3 ADC1Value[2] = ( AD1DR2 >> 6 ) & 0x3FF;
182 3 break;
183 3 case 0x08:
184 3 ADC1Value[3] = ( AD1DR3 >> 6 ) & 0x3FF;
185 3 break;
186 3 case 0x10:
187 3 ADC1Value[4] = ( AD1DR4 >> 6 ) & 0x3FF;
188 3 break;
189 3 case 0x20:
190 3 ADC1Value[5] = ( AD1DR5 >> 6 ) & 0x3FF;
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 4
191 3 break;
192 3 case 0x40:
193 3 ADC1Value[6] = ( AD1DR6 >> 6 ) & 0x3FF;
194 3 break;
195 3 case 0x80:
196 3 ADC1Value[7] = ( AD1DR7 >> 6 ) & 0x3FF;
197 3 break;
198 3 default:
199 3 break;
200 3 }
201 2 AD1CR &= 0xF8FFFFFF; /* stop ADC now */
202 2 ADC1IntDone = 1;
203 2 }
204 1
205 1 IDISABLE;
206 1 VICVectAddr = 0; /* Acknowledge Interrupt */
207 1 }
208 #endif
209
210 /*****************************************************************************
211 ** Function name: ADCInit
212 **
213 ** Descriptions: initialize ADC channel
214 **
215 ** parameters: ADC clock rate
216 ** Returned value: true or false
217 **
218 *****************************************************************************/
219 DWORD ADCInit( DWORD ADC_Clk )
220 {
221 1 /* all the related pins are set to ADC inputs, AD0.1~4, AD1.0~7 */
222 1 PINSEL0 = 0x0F333F00;
223 1 PINSEL1 = 0x15541800;
224 1
225 1 AD0CR = ( 0x01 << 0 ) | // SEL=1,select channel 0, 1 to 4 on ADC0
226 1 ( ( Fpclk / ADC_Clk - 1 ) << 8 ) | // CLKDIV = Fpclk / 1000000 - 1
227 1 ( 0 << 16 ) | // BURST = 0, no BURST, software controlled
228 1 ( 0 << 17 ) | // CLKS = 0, 11 clocks/10 bits
229 1 ( 1 << 21 ) | // PDN = 1, normal operation
230 1 ( 0 << 22 ) | // TEST1:0 = 00
231 1 ( 0 << 24 ) | // START = 0 A/D conversion stops
232 1 ( 0 << 27 ); /* EDGE = 0 (CAP/MAT singal falling,trigger A/D
233 1 conversion) */
234 1 AD1CR = ( 0x01 << 0 ) | // SEL=1,select channel 0, 0 to 7 on ADC1
235 1 ( ( Fpclk / ADC_Clk - 1 ) << 8 ) | // CLKDIV = Fpclk / 1000000 - 1
236 1 ( 0 << 16 ) | // BURST = 0, no BURST, software controlled
237 1 ( 0 << 17 ) | // CLKS = 0, 11 clocks/10 bits
238 1 ( 1 << 21 ) | // PDN = 1, normal operation
239 1 ( 0 << 22 ) | // TEST1:0 = 00
240 1 ( 0 << 24 ) | // START = 0 A/D conversion stops
241 1 ( 0 << 27 ); /* EDGE = 0 (CAP/MAT singal falling,trigger A/D
242 1 conversion) */
243 1
244 1 /* If POLLING, no need to do the following */
245 1 #if ADC_INTERRUPT_FLAG
246 1 AD0INTEN = 0x11E; // Enable all interrupts
247 1 AD1INTEN = 0x1FF;
248 1
249 1 if ( install_irq( ADC0_INT, (void *)ADC0Handler ) == FALSE )
250 1 {
251 2 return (FALSE);
252 2 }
253 1 if ( install_irq( ADC1_INT, (void *)ADC1Handler ) == FALSE )
254 1 {
255 2 return (FALSE);
256 2 }
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 5
257 1 #endif
258 1
259 1 return (TRUE);
260 1 }
261
262 /*****************************************************************************
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