📄 wave.rpt
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Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
B53 8/16( 50%) 0/16( 0%) 8/16( 50%) 1/2 2/6 10/104( 9%)
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 19/141 ( 13%)
Total logic cells used: 96/4992 ( 1%)
Total embedded cells used: 8/192 ( 4%)
Total EABs used: 1/12 ( 8%)
Average fan-in: 3.32/4 ( 83%)
Total fan-in: 319/19968 ( 1%)
Total input pins required: 11
Total input I/O cell registers required: 0
Total output pins required: 9
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 96
Total flipflops required: 27
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 25/4992 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 8 8 8 5 0 0 0 8 0 0 8 0 0 0 0 8 0 0 0 8 8 0 0 0 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77/8
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 8 0 0 8 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 8 8 5 0 0 0 8 0 0 8 8 0 0 8 11 0 0 0 8 8 0 0 0 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 96/8
Device-Specific Information: f:\khf1-5\exa14\wave\wave.rpt
wave
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
103 - - - 02 INPUT ^ 0 0 0 1 inb0
104 - - - 01 INPUT ^ 0 0 0 1 inb1
111 - - L -- INPUT ^ 0 0 0 1 inb2
112 - - L -- INPUT ^ 0 0 0 1 inb3
113 - - K -- INPUT ^ 0 0 0 1 inb4
114 - - K -- INPUT ^ 0 0 0 1 inb5
115 - - J -- INPUT ^ 0 0 0 1 inb6
116 - - I -- INPUT ^ 0 0 0 2 inb7
183 - - - -- INPUT G ^ 0 0 0 0 inclk
128 - - E -- INPUT ^ 0 0 0 13 mode0
127 - - F -- INPUT ^ 0 0 0 13 mode1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\khf1-5\exa14\wave\wave.rpt
wave
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
93 - - - 14 OUTPUT 0 0 0 0 cs
131 - - E -- OUTPUT 0 1 0 0 da0
132 - - E -- OUTPUT 0 1 0 0 da1
133 - - D -- OUTPUT 0 1 0 0 da2
134 - - D -- OUTPUT 0 1 0 0 da3
135 - - D -- OUTPUT 0 1 0 0 da4
136 - - C -- OUTPUT 0 1 0 0 da5
139 - - C -- OUTPUT 0 1 0 0 da6
140 - - C -- OUTPUT 0 1 0 0 da7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\khf1-5\exa14\wave\wave.rpt
wave
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - K 12 DFFE + 1 2 0 19 f
- 7 - K 15 DFFE + 0 1 0 4 fp0
- 6 - K 15 DFFE + 0 2 0 3 fp1
- 8 - K 15 DFFE + 0 3 0 2 fp2
- 1 - K 16 DFFE + 0 2 0 4 fp3
- 2 - K 16 DFFE + 0 3 0 3 fp4
- 3 - K 12 DFFE + 0 3 0 2 fp5
- 6 - K 12 DFFE + 0 2 0 2 fp6
- 7 - K 12 DFFE + 0 3 0 2 fp7
- 4 - B 11 DFFE 0 4 0 5 md0
- 8 - B 03 DFFE 0 3 0 4 md1
- 7 - B 03 DFFE 0 4 0 3 md2
- 6 - B 03 DFFE 0 4 0 2 md3
- 6 - B 26 DFFE 0 3 0 3 md4
- 5 - B 26 DFFE 0 4 0 2 md5
- 7 - B 08 DFFE 0 3 0 3 md6
- 6 - B 08 DFFE 0 4 0 2 md7
- 2 - B 08 DFFE 0 3 0 3 md8
- - 3 B -- MEM_SGMT 0 10 0 1 |sin:msin|LPM_ROM:1|altrom:srom|segment0_0
- - 10 B -- MEM_SGMT 0 10 0 1 |sin:msin|LPM_ROM:1|altrom:srom|segment0_1
- - 2 B -- MEM_SGMT 0 10 0 1 |sin:msin|LPM_ROM:1|altrom:srom|segment0_2
- - 9 B -- MEM_SGMT 0 10 0 1 |sin:msin|LPM_ROM:1|altrom:srom|segment0_3
- - 1 B -- MEM_SGMT 0 10 0 1 |sin:msin|LPM_ROM:1|altrom:srom|segment0_4
- - 12 B -- MEM_SGMT 0 10 0 1 |sin:msin|LPM_ROM:1|altrom:srom|segment0_5
- - 4 B -- MEM_SGMT 0 10 0 1 |sin:msin|LPM_ROM:1|altrom:srom|segment0_6
- - 11 B -- MEM_SGMT 0 10 0 1 |sin:msin|LPM_ROM:1|altrom:srom|segment0_7
- 3 - B 11 DFFE 0 5 0 12 st
- 2 - B 01 DFFE 0 5 1 6 :66
- 5 - B 21 DFFE 0 4 1 4 :67
- 7 - B 20 DFFE 0 5 1 6 :68
- 1 - B 20 DFFE 0 4 1 7 :69
- 8 - B 16 DFFE 0 4 1 6 :70
- 7 - B 02 DFFE 0 5 1 6 :71
- 1 - B 26 DFFE 0 4 1 7 :72
- 5 - B 11 DFFE 0 4 1 8 :73
- 1 - K 15 OR2 ! 2 2 0 1 :105
- 2 - K 15 OR2 ! 1 2 0 1 :112
- 3 - K 15 OR2 ! 1 2 0 1 :120
- 4 - K 15 OR2 ! 1 2 0 1 :127
- 1 - K 12 OR2 ! 1 2 0 1 :134
- 2 - K 12 OR2 ! 1 2 0 2 :142
- 8 - K 12 OR2 ! 1 2 0 8 :149
- 5 - K 15 AND2 0 3 0 4 :162
- 3 - K 16 AND2 0 2 0 1 :166
- 4 - K 12 AND2 0 4 0 2 :174
- 2 - B 04 AND2 ! 2 0 0 2 :202
- 4 - B 01 AND2 ! 2 0 0 3 :251
- 5 - B 01 AND2 0 2 0 3 :254
- 3 - B 01 AND2 0 3 0 9 :271
- 1 - B 02 AND2 0 3 0 1 :299
- 4 - B 02 AND2 0 4 0 4 :303
- 8 - B 21 AND2 0 3 0 1 :311
- 4 - B 21 AND2 0 4 0 3 :315
- 6 - B 01 OR2 0 4 0 8 :363
- 3 - B 02 OR2 0 3 0 1 :374
- 2 - B 02 OR2 0 3 0 4 :376
- 7 - B 16 OR2 0 2 0 1 :381
- 3 - B 20 OR2 0 4 0 1 :390
- 1 - B 21 OR2 0 4 0 2 :392
- 2 - B 21 OR2 0 2 0 2 :397
- 8 - B 01 AND2 0 4 0 1 :418
- 1 - B 11 AND2 2 1 0 4 :425
- 1 - B 08 AND2 ! 0 2 0 3 :457
- 2 - B 11 AND2 0 2 0 1 :461
- 4 - B 04 AND2 ! 2 0 0 20 :534
- 2 - B 26 AND2 0 2 0 8 :536
- 3 - B 04 AND2 0 2 0 8 :538
- 1 - B 03 AND2 0 2 0 8 :540
- 3 - B 03 AND2 0 2 0 8 :542
- 4 - B 03 AND2 0 2 0 8 :544
- 3 - B 26 AND2 0 2 0 8 :546
- 4 - B 26 AND2 0 2 0 8 :548
- 3 - B 08 AND2 0 2 0 8 :550
- 4 - B 08 AND2 0 2 0 8 :552
- 5 - B 08 AND2 0 2 0 8 :554
- 6 - B 11 OR2 s 2 2 0 1 ~557~1
- 7 - B 11 OR2 s 0 4 0 1 ~557~2
- 1 - B 01 OR2 s 0 4 0 6 ~560~1
- 1 - B 16 OR2 s 2 2 0 1 ~560~2
- 6 - B 16 OR2 s 0 4 0 1 ~560~3
- 7 - B 26 OR2 s 0 4 0 1 ~560~4
- 5 - B 02 OR2 s 2 2 0 1 ~563~1
- 6 - B 02 OR2 s 0 4 0 1 ~563~2
- 8 - B 02 OR2 s 0 4 0 1 ~563~3
- 2 - B 16 OR2 s 2 2 0 1 ~566~1
- 3 - B 16 OR2 s 0 4 0 1 ~566~2
- 4 - B 16 OR2 s 0 4 0 1 ~566~3
- 2 - B 20 OR2 s 2 2 0 1 ~569~1
- 5 - B 20 OR2 s 0 4 0 1 ~569~2
- 5 - B 16 OR2 s 0 4 0 1 ~569~3
- 4 - B 20 OR2 s 2 2 0 1 ~572~1
- 6 - B 20 OR2 s 0 4 0 1 ~572~2
- 8 - B 20 OR2 s 0 4 0 1 ~572~3
- 3 - B 21 OR2 s 2 2 0 1 ~575~1
- 6 - B 21 OR2 s 0 4 0 1 ~575~2
- 7 - B 21 OR2 s 0 4 0 1 ~575~3
- 7 - B 01 OR2 s 0 4 0 1 ~578~1
- 5 - B 04 OR2 s 2 2 0 1 ~578~2
- 1 - B 04 OR2 s 2 2 0 1 ~578~3
- 5 - B 03 AND2 0 2 0 1 :606
- 2 - B 03 OR2 ! 0 4 0 3 :614
- 8 - B 26 OR2 ! 0 3 0 3 :622
- 8 - B 08 OR2 ! 0 3 0 3 :630
- 8 - B 11 OR2 s 0 4 0 7 ~650~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\khf1-5\exa14\wave\wave.rpt
wave
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 40/208( 19%) 12/104( 11%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 3/104( 2%) 0/104( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
D: 0/208( 0%) 3/104( 2%) 0/104( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
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