📄 madev_initial.c.bak
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#include "pccdef.h"
#include "predef.h"
#include "Madev_initial.h"
#include "Machdep.h"
/****************************************************************/
/* Function Name : MaDevDrv_PLLSetting */
/* Description : set cofficient of division for PLL circuit */
/* Note : make as near as the reference value of PLL */
/* output frequence (55.296MHz) */
/****************************************************************/
void MaDevDrv_PLLSetting(void)
{
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG ); /* Bank #1 */
machdep_WriteDataReg( 0x01 );
machdep_WriteStatusFlagReg( MA_PLL_SETTING_1_REG );
machdep_WriteDataReg( (UINT8)(MA_ADJUST1_VALUE & 0x1F) );
machdep_WriteStatusFlagReg( MA_PLL_SETTING_2_REG );
machdep_WriteDataReg( (UINT8)(MA_ADJUST2_VALUE & 0x7F) );
machdep_WriteStatusFlagReg( 0x80 ); /* permit IRQ interrupt */
}
/********************************************************************/
/* Function Name : MaDevDrv_PowerManagement */
/* Description : It's a primary part of Hardware Initialize */
/* Note : mode select 0~3 */
/* 0: Hardware initialize sequence (power down) */
/* 1: Hardware initialize sequence (normal) */
/* 2: Power down change sequence */
/* 3: Power down release sequence */
/* Every mode contain the process of analog volume. */
/* The setting value of SpeakPhone is MUTE, */
/* so the HeadPhone is available. */
/********************************************************************/
SINT32 MaDevDrv_PowerManagement
(
UINT8 mode /* operation mode */
)
{
UINT8 count; /* loop counter */
SINT32 result = MASMW_SUCCESS; /* result of function */
switch ( mode )
{
case 0:
/* sequence of hardware initialize when power downed */
/* set BANK bits of REG_ID #4 basic setting register to '0' */
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG );
machdep_WriteDataReg( 0x00 );
/* set DP0 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 | MA_DP2 | MA_DP1 );
/* set PLLPD bit of power management (A) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_ANALOG_REG );
machdep_WriteDataReg( MA_AP4R | MA_AP4L | MA_AP3 | MA_AP2 | MA_AP1 | MA_AP0 );
/* wait 10ms */
machdep_Wait( 10 * 1000 * 1000 );
/* set DP1 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 | MA_DP2 );
/* set DP2 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteDataReg( MA_DP3 );
for ( count = 0; count < 10; count++ )
{
/* set RST bit of REG_ID #4 basic setting register to '1' */
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG );
machdep_WriteDataReg( 0x80 );
/* set RST bit of REG_ID #4 basic setting register to '0' */
machdep_WriteDataReg( 0x00 );
/* verify the initialized registers by software reset */
result = MaDevDrv_VerifyRegisters();
if ( result == MASMW_SUCCESS ) break;
}
/* wait 41.7us */
machdep_Wait( 41700 );
/* set DP2 bit of REG_ID #5 power management (D) setting register to '1' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 | MA_DP2 );
/* set DP1 bit of REG_ID #5 power management (D) setting register to '1' */
machdep_WriteDataReg( MA_DP3 | MA_DP2 | MA_DP1 );
/* set PLLPD bit of REG_ID #6 power management (A) setting register to '1' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_ANALOG_REG );
machdep_WriteDataReg( MA_PLLPD | MA_AP4R | MA_AP4L | MA_AP3 | MA_AP2 | MA_AP1 | MA_AP0 );
/* set DP0 bit of REG_ID #5 power management (D) setting register to '1' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 | MA_DP2 | MA_DP1 | MA_DP0 );
/* set Analog volume to MUTE */
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG ); /* Bank #0 */
machdep_WriteDataReg( 0x00 );
machdep_WriteStatusFlagReg( MA_ANALOG_EQVOL_REG ); /* set EQ volume */
machdep_WriteDataReg( (UINT8)(MA_MUTE & 0x1F) );
machdep_WriteStatusFlagReg( MA_ANALOG_HPVOL_L_REG ); /* set Headphone volume */
machdep_WriteDataReg( (UINT8)((MA_MONO<<7) | (MA_MUTE&0x1F)) );
machdep_WriteStatusFlagReg( MA_ANALOG_HPVOL_R_REG );
machdep_WriteDataReg( (UINT8)(MA_MUTE & 0x1F) );
machdep_WriteStatusFlagReg( MA_ANALOG_SPVOL_REG ); /* set speakphone to MUTE */
machdep_WriteDataReg( (UINT8)((MA_VSEL<<6) | (MA_MUTE&0x1F)) );
/* enable interrupt if needed */
machdep_WriteStatusFlagReg( 0x80 );
break;
case 1:
/* sequence of hardware initialize when normal */
/* set BANK bits of REG_ID #4 basic setting register to '0' */
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG );
machdep_WriteDataReg( 0x00 );
/* set DP0 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 | MA_DP2 | MA_DP1 );
/* set PLLPD and AP0 bits of REG_ID #6 power management (A) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_ANALOG_REG );
machdep_WriteDataReg( MA_AP4R | MA_AP4L | MA_AP3 | MA_AP2 | MA_AP1 );
machdep_Wait( 10 * 1000 * 1000 );
/* set DP1 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 | MA_DP2 );
/* set DP2 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteDataReg( MA_DP3 );
for ( count = 0; count < 10; count++ )
{
/* set RST bit of REG_ID #4 basic setting register to '1' */
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG );
machdep_WriteDataReg( 0x80 );
/* set RST bit of REG_ID #4 basic setting register to '0' */
machdep_WriteDataReg( 0x00 );
/* verify the initialized registers by software reset */
result = MaDevDrv_VerifyRegisters();
if ( result == MASMW_SUCCESS ) break;
}
if( result != MASMW_SUCCESS)
{
printf_uart2("\n Verify Reg failure!!!");
return 0;
}
/* wait 41.7us */
machdep_Wait( 41700 );
/* set DP3 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( 0x00 );
/* set AP1, AP3 and AP4 bits of REG_ID #6 power management (A) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_ANALOG_REG );
machdep_WriteDataReg( MA_AP2 );
/* wait 10us */
machdep_Wait( 10 * 1000 );
/* set AP2,AP1 bit of REG_ID #6 power management (A) setting register to '1'(Headphone mode)*/
machdep_WriteDataReg( MA_AP2 | MA_AP1 );
/* set Analog volume */
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG ); /* Bank #0 */
machdep_WriteDataReg( 0x00 );
machdep_WriteStatusFlagReg( MA_ANALOG_EQVOL_REG ); /* set EQ volume */
machdep_WriteDataReg( (UINT8)(MA_ANALOG_VOL & 0x1F) );
machdep_WriteStatusFlagReg( MA_ANALOG_HPVOL_L_REG ); /* set Headphone volume */
machdep_WriteDataReg( (UINT8)((MA_MONO<<7) | (MA_ANALOG_VOL&0x1F)) );
machdep_WriteStatusFlagReg( MA_ANALOG_HPVOL_R_REG );
machdep_WriteDataReg( (UINT8)(MA_ANALOG_VOL & 0x1F) );
machdep_WriteStatusFlagReg( MA_ANALOG_SPVOL_REG ); /* SP to MUTE(Headphone mode) */
machdep_WriteDataReg( (UINT8)((MA_VSEL<<6) | (MA_MUTE&0x1F)) );
/* enable interrupt */
machdep_WriteStatusFlagReg( 0x80 );
/* normal */
break;
case 2:
/* sequence of power down */
/* set BANK bits of REG_ID #4 basic setting register to '0' */
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG );
machdep_WriteDataReg( 0x00 );
/* set DP3 bit of REG_ID #5 power management (D) setting register to '1' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 );
/* set DP2 bit of REG_ID #5 power management (D) setting register to '1' */
machdep_WriteDataReg( MA_DP3 | MA_DP2 );
/* set DP1 bit of REG_ID #5 power management (D) setting register to '1' */
machdep_WriteDataReg( MA_DP3 | MA_DP2 | MA_DP1 );
/* set AP1, AP2, AP3, AP4 and PLLPD bits of REG_ID #6 power management (A) setting register to '1' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_ANALOG_REG );
machdep_WriteDataReg( MA_PLLPD | MA_AP4R | MA_AP4L | MA_AP3 | MA_AP2 | MA_AP1 | MA_AP0 );
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