omap_mpu_addr.h

YAMAHA的铃音芯片的测试程序

#define OMAP_WATCHDOG_READ_TIM_WD       		   *((volatile unsigned long *)(0xFFFEC808))
#define OMAP_WATCHDOG_TIMER_MODE_WD     		   *((volatile unsigned long *)(0xFFFEC80C))


///////////////////////////////////*/
// 32K Hz Watchdog Timer Registers */
///////////////////////////////////*/     
#define WATCHDOG_32K_WIDR     		             *((volatile unsigned long *)(0xFFFEB000)) 
#define WATCHDOG_32K_SYSCONFIG                 *((volatile unsigned long *)(0xFFFEB010)) 
#define WATCHDOG_32K_SYSSTATUS                 *((volatile unsigned long *)(0xFFFEB014)) 
#define WATCHDOG_32K_WCLR                      *((volatile unsigned long *)(0xFFFEB024)) 
#define WATCHDOG_32K_WCRR                      *((volatile unsigned long *)(0xFFFEB028)) 
#define WATCHDOG_32K_WLDR                      *((volatile unsigned long *)(0xFFFEB02C)) 
#define WATCHDOG_32K_WTGR                      *((volatile unsigned long *)(0xFFFEB030)) 
#define WATCHDOG_32K_WWPS                      *((volatile unsigned long *)(0xFFFEB034))  
#define WATCHDOG_32K_WSPR                      *((volatile unsigned long *)(0xFFFEB048)) 
 
  
///////////////////////////////////*/
// Secure Watchdog Timer Registers */
///////////////////////////////////*/     
#define SECURE_WATCHDOG_WIDR     		           *((volatile unsigned long *)(0xFFFEA800)) 
#define SECURE_WATCHDOG_SYSCONFIG              *((volatile unsigned long *)(0xFFFEA810)) 
#define SECURE_WATCHDOG_SYSSTATUS              *((volatile unsigned long *)(0xFFFEA814)) 
#define SECURE_WATCHDOG_WCLR                   *((volatile unsigned long *)(0xFFFEA824)) 
#define SECURE_WATCHDOG_WCRR                   *((volatile unsigned long *)(0xFFFEA828)) 
#define SECURE_WATCHDOG_WLDR                   *((volatile unsigned long *)(0xFFFEA82C)) 
#define SECURE_WATCHDOG_WTGR                   *((volatile unsigned long *)(0xFFFEA830)) 
#define SECURE_WATCHDOG_WWPS                   *((volatile unsigned long *)(0xFFFEA834)) 
#define SECURE_WATCHDOG_32K_WSPR                      *((volatile unsigned long *)(0xFFFEA848))


//////////////////////////*/
// DSP OS Timer Registers */ 
//////////////////////////*/
// Timer 1 */
#define DSP_CNTL_TIMER1		                     *((volatile unsigned short *)(0xE1005000)) 
#define DSP_LOAD_TIMER1_LO                     *((volatile unsigned short *)(0xE1005004)) 
#define DSP_LOAD_TIMER1_HI                     *((volatile unsigned short *)(0xE1005006)) 
#define DSP_READ_TIMER1_LO                     *((volatile unsigned short *)(0xE1005008)) 
#define DSP_READ_TIMER1_HI                     *((volatile unsigned short *)(0xE100500A)) 

// Timer 2 */                                                                               
#define DSP_CNTL_TIMER2		                     *((volatile unsigned short *)(0xE1005800)) 
#define DSP_LOAD_TIMER2_LO                     *((volatile unsigned short *)(0xE1005804)) 
#define DSP_LOAD_TIMER2_HI                     *((volatile unsigned short *)(0xE1005806)) 
#define DSP_READ_TIMER2_LO                     *((volatile unsigned short *)(0xE1005808)) 
#define DSP_READ_TIMER2_HI                     *((volatile unsigned short *)(0xE100580A)) 

// Timer 3 */                                                                               
#define DSP_CNTL_TIMER3		                     *((volatile unsigned short *)(0xE1006000)) 
#define DSP_LOAD_TIMER3_LO                     *((volatile unsigned short *)(0xE1006004)) 
#define DSP_LOAD_TIMER3_HI                     *((volatile unsigned short *)(0xE1006006)) 
#define DSP_READ_TIMER3_LO                     *((volatile unsigned short *)(0xE1006008)) 
#define DSP_READ_TIMER3_HI                     *((volatile unsigned short *)(0xE100600A)) 

////////////////////////////////*/
// 32-kHz synchronization Timer */
////////////////////////////////*/
//MPU 32-kHz synchronization Timer*/  
#define MPU_32KSYNCNT_REV                      *((volatile unsigned long *)(0xFFFBC400))
#define MPU_CR                                 *((volatile unsigned long *)(0xFFFBC410))
/*DSP 32-kHz synchronization Timer*/                                                    
#define DSP_32KSYNCNT_REV                      *((volatile unsigned long *)(0xE101C400))
#define DSP_CR                                 *((volatile unsigned long *)(0xE101C410))



//////////////////////////*/
// MPU interrupt register */
//////////////////////////*/
// MPU Level 1 Interrupt Handler Registers */                                                               
#define MPU_L1_ITR                      *((volatile unsigned long *)(0xFFFECB00))                                                                         
#define MPU_L1_MIR                      *((volatile unsigned long *)(0xFFFECB04))
#define MPU_L1_SIR_IRQ                  *((volatile unsigned long *)(0xFFFECB10))                                                                        
#define MPU_L1_SIR_FIQ                  *((volatile unsigned long *)(0xFFFECB14))                                                                        
#define MPU_L1_CONTROL_REG              *((volatile unsigned long *)(0xFFFECB18))                                                                         
#define MPU_L1_ILR0                     *((volatile unsigned long *)(0xFFFECB1C))                                                                         
#define MPU_L1_ILR1 			              *((volatile unsigned long *)(0xFFFECB20)) 		                                                               																																											
#define MPU_L1_ILR2 			              *((volatile unsigned long *)(0xFFFECB24)) 																																																				
#define MPU_L1_ILR3 			              *((volatile unsigned long *)(0xFFFECB28)) 																																																				
#define MPU_L1_ILR4 			              *((volatile unsigned long *)(0xFFFECB2C)) 																																																				
#define MPU_L1_ILR5 			              *((volatile unsigned long *)(0xFFFECB30)) 																																																				
#define MPU_L1_ILR6 			              *((volatile unsigned long *)(0xFFFECB34)) 																																																				
#define MPU_L1_ILR7 			              *((volatile unsigned long *)(0xFFFECB38)) 																																																				
#define MPU_L1_ILR8 			              *((volatile unsigned long *)(0xFFFECB3C)) 																																																				
#define MPU_L1_ILR9 			              *((volatile unsigned long *)(0xFFFECB40)) 																																																				
#define MPU_L1_ILR10			              *((volatile unsigned long *)(0xFFFECB44)) 																																																				
#define MPU_L1_ILR11			              *((volatile unsigned long *)(0xFFFECB48)) 																																																				
#define MPU_L1_ILR12			              *((volatile unsigned long *)(0xFFFECB4C)) 																																																				
#define MPU_L1_ILR13			              *((volatile unsigned long *)(0xFFFECB50)) 																																																				
#define MPU_L1_ILR14			              *((volatile unsigned long *)(0xFFFECB54)) 																																																				
#define MPU_L1_ILR15			              *((volatile unsigned long *)(0xFFFECB58)) 																																																				
#define MPU_L1_ILR16			              *((volatile unsigned long *)(0xFFFECB5C)) 																																																				
#define MPU_L1_ILR17			              *((volatile unsigned long *)(0xFFFECB60)) 																																																				
#define MPU_L1_ILR18			              *((volatile unsigned long *)(0xFFFECB64)) 																																																				
#define MPU_L1_ILR19			              *((volatile unsigned long *)(0xFFFECB68)) 																																																				
#define MPU_L1_ILR20			              *((volatile unsigned long *)(0xFFFECB6C)) 																																																				
#define MPU_L1_ILR21			              *((volatile unsigned long *)(0xFFFECB70)) 																																																				
#define MPU_L1_ILR22			              *((volatile unsigned long *)(0xFFFECB74)) 																																																				
#define MPU_L1_ILR23			              *((volatile unsigned long *)(0xFFFECB78)) 																																																				
#define MPU_L1_ILR24			              *((volatile unsigned long *)(0xFFFECB7C)) 																																																				
#define MPU_L1_ILR25			              *((volatile unsigned long *)(0xFFFECB80)) 																																																				
#define MPU_L1_ILR26			              *((volatile unsigned long *)(0xFFFECB84)) 																																																				
#define MPU_L1_ILR27			              *((volatile unsigned long *)(0xFFFECB88)) 																																																				
#define MPU_L1_ILR28			              *((volatile unsigned long *)(0xFFFECB8C)) 																																																				
#define MPU_L1_ILR29			              *((volatile unsigned long *)(0xFFFECB90)) 																																																				
#define MPU_L1_ILR30			              *((volatile unsigned long *)(0xFFFECB94)) 																																																				
#define MPU_L1_ILR31			              *((volatile unsigned long *)(0xFFFECB98)) 																																																				
#define MPU_L1_SIR 			                *((volatile unsigned long *)(0xFFFECB9C)) 
#define MPU_L1_GMR		                  *((volatile unsigned long *)(0xFFFECBA0)) 
            																																																							
/* MPU Level 2 Interrupt Handler Registers */  /*changed in 3/5/2004*/      
#define MPU_L2_SIR_IRQ                  *((volatile unsigned long *)(0xFFFE0010))                                                                         
#define MPU_L2_SIR_FIQ                  *((volatile unsigned long *)(0xFFFE0014))                                                                        
#define MPU_L2_CONTROL_REG              *((volatile unsigned long *)(0xFFFE0018))