lpc11xx.h

LPC1114_例程和教程

/*********************************************************************************************************
**   $Id:: LPC11xx.h 3635 2010-06-02 00:31:46Z usb00423 $
**   Project: NXP LPC11xx software example  
**
**   Description:
**     CMSIS Cortex-M0 Core Peripheral Access Layer Header File for 
**     NXP LPC11xx Device Series 
**
**--------------------------------------------------------------------------------------------------------
** Software that is described herein is for illustrative purposes only
** which provides customers with programming information regarding the
** products. This software is supplied "AS IS" without any warranties.
** NXP Semiconductors assumes no responsibility or liability for the
** use of the software, conveys no license or title under any patent,
** copyright, or mask work right to the product. NXP Semiconductors
** reserves the right to make changes in the software without
** notification. NXP Semiconductors also make no representation or
** warranty that such application will be suitable for the specified
** use without further testing or modification.
*********************************************************************************************************/
#ifndef __LPC11xx_H__
#define __LPC11xx_H__

#ifdef __cplusplus
 extern "C" {
#endif 

/*
 *  @addtogroup LPC11xx_Definitions LPC11xx Definitions
 *  This file defines all structures and symbols for LPC11xx:
 *    - Registers and bitfields
 *    - peripheral base address
 *    - peripheral ID
 *    - PIO definitions
 *  @{
 */


/*********************************************************************************************************
  ----------------------------------Processor and Core Peripherals---------------------------------------
*********************************************************************************************************/
/*
 *  @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions
 *  Configuration of the Cortex-M0 Processor and Core Peripherals
 *  @{
 */

/*********************************************************************************************************
  Interrupt Number Definition
*********************************************************************************************************/
typedef enum IRQn
{
    /*
     *  Cortex-M0 Processor Exceptions Numbers
     */
    NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                             */
    HardFault_IRQn                = -13,      /*!< 3 Cortex-M0 Hard Fault Interrupt                     */
    SVCall_IRQn                   = -5,       /*!< 11 Cortex-M0 SV Call Interrupt                       */
    PendSV_IRQn                   = -2,       /*!< 14 Cortex-M0 Pend SV Interrupt                       */
    SysTick_IRQn                  = -1,       /*!< 15 Cortex-M0 System Tick Interrupt                   */

    /*
     *  LPC11xx Specific Interrupt Numbers
     */
    WAKEUP0_IRQn                  = 0,        /*!< All I/O pins can be used as wakeup source.           */
    WAKEUP1_IRQn                  = 1,        /*!< There are 13 pins in total for LPC11xx               */
    WAKEUP2_IRQn                  = 2,
    WAKEUP3_IRQn                  = 3,
    WAKEUP4_IRQn                  = 4,   
    WAKEUP5_IRQn                  = 5,        
    WAKEUP6_IRQn                  = 6,        
    WAKEUP7_IRQn                  = 7,        
    WAKEUP8_IRQn                  = 8,        
    WAKEUP9_IRQn                  = 9,        
    WAKEUP10_IRQn                 = 10,       
    WAKEUP11_IRQn                 = 11,       
    WAKEUP12_IRQn                 = 12,       
    CAN_IRQn                      = 13,       /*!< CAN Interrupt                                        */
    SSP1_IRQn                     = 14,       /*!< SSP1 Interrupt                                       */
    I2C_IRQn                      = 15,       /*!< I2C Interrupt                                        */
    TIMER_16_0_IRQn               = 16,       /*!< 16-bit Timer0 Interrupt                              */
    TIMER_16_1_IRQn               = 17,       /*!< 16-bit Timer1 Interrupt                              */
    TIMER_32_0_IRQn               = 18,       /*!< 32-bit Timer0 Interrupt                              */
    TIMER_32_1_IRQn               = 19,       /*!< 32-bit Timer1 Interrupt                              */
    SSP0_IRQn                     = 20,       /*!< SSP0 Interrupt                                       */
    UART_IRQn                     = 21,       /*!< UART Interrupt                                       */
    ADC_IRQn                      = 24,       /*!< A/D Converter Interrupt                              */
    WDT_IRQn                      = 25,       /*!< Watchdog timer Interrupt                             */
    BOD_IRQn                      = 26,       /*!< Brown Out Detect(BOD) Interrupt                      */
    EINT3_IRQn                    = 28,       /*!< External Interrupt 3 Interrupt                       */
    EINT2_IRQn                    = 29,       /*!< External Interrupt 2 Interrupt                       */
    EINT1_IRQn                    = 30,       /*!< External Interrupt 1 Interrupt                       */
    EINT0_IRQn                    = 31,       /*!< External Interrupt 0 Interrupt                       */
} IRQn_Type;


/*********************************************************************************************************
  Processor and Core Peripheral Section
*********************************************************************************************************/
/*
 *  Configuration of the Cortex-M3 Processor and Core Peripherals
 */
#define __MPU_PRESENT             0           /*!< MPU present or not                                   */
#define __NVIC_PRIO_BITS          3           /*!< Number of Bits used for Priority Levels              */
#define __Vendor_SysTickConfig    0           /*!< Set to 1 if different SysTick Config is used         */

/*
 *  end of group LPC11xx_CMSIS
 *  @}
 */


#include "core_cm0.h"                         /* Cortex-M0 processor and core peripherals               */
#include "system_LPC11xx.h"                   /* System Header                                          */


/*********************************************************************************************************
  ---------------------------Device Specific Peripheral Registers structures-----------------------------
*********************************************************************************************************/
#if defined ( __CC_ARM   )
#pragma anon_unions
#endif

/*********************************************************************************************************
  System Control (SYSCON)
*********************************************************************************************************/
/*
 *  @addtogroup LPC11xx_SYSCON LPC11xx System Control Block 
 *  @{
 */
typedef struct
{
    __IO uint32_t SYSMEMREMAP;            /*!< Offset: 0x000 System memory remap (R/W)                  */
    __IO uint32_t PRESETCTRL;             /*!< Offset: 0x004 Peripheral reset control (R/W)             */
    __IO uint32_t SYSPLLCTRL;             /*!< Offset: 0x008 System PLL control (R/W)                   */
    __IO uint32_t SYSPLLSTAT;             /*!< Offset: 0x00C System PLL status (R/ )                    */
         uint32_t RESERVED0[4];

    __IO uint32_t SYSOSCCTRL;             /*!< Offset: 0x020 System oscillator control (R/W)            */
    __IO uint32_t WDTOSCCTRL;             /*!< Offset: 0x024 Watchdog oscillator control (R/W)          */
    __IO uint32_t IRCCTRL;                /*!< Offset: 0x028 IRC control (R/W)                          */
         uint32_t RESERVED1[1];
    __IO uint32_t SYSRESSTAT;             /*!< Offset: 0x030 System reset status Register (R/ )         */
         uint32_t RESERVED2[3];
    __IO uint32_t SYSPLLCLKSEL;           /*!< Offset: 0x040 System PLL clock source select (R/W)       */
    __IO uint32_t SYSPLLCLKUEN;           /*!< Offset: 0x044 System PLL clock source update enable (R/W)*/
         uint32_t RESERVED3[10];

    __IO uint32_t MAINCLKSEL;             /*!< Offset: 0x070 Main clock source select (R/W)             */
    __IO uint32_t MAINCLKUEN;             /*!< Offset: 0x074 Main clock source update enable (R/W)      */
    __IO uint32_t SYSAHBCLKDIV;           /*!< Offset: 0x078 System AHB clock divider (R/W)             */
         uint32_t RESERVED4[1];

    __IO uint32_t SYSAHBCLKCTRL;          /*!< Offset: 0x080 System AHB clock control (R/W)             */
         uint32_t RESERVED5[4];
    __IO uint32_t SSP0CLKDIV;             /*!< Offset: 0x094 SSP0 clock divider (R/W)                   */
    __IO uint32_t UARTCLKDIV;             /*!< Offset: 0x098 UART clock divider (R/W)                   */
    __IO uint32_t SSP1CLKDIV;             /*!< Offset: 0x09C SSP1 clock divider (R/W)                   */
         uint32_t RESERVED6[4];

    __IO uint32_t SYSTICKCLKDIV;          /*!< Offset: 0x0B0 SYSTICK clock divider (R/W)                */
         uint32_t RESERVED7[7];

    __IO uint32_t WDTCLKSEL;              /*!< Offset: 0x0D0 WDT clock source select (R/W)              */
    __IO uint32_t WDTCLKUEN;              /*!< Offset: 0x0D4 WDT clock source update enable (R/W)       */
    __IO uint32_t WDTCLKDIV;              /*!< Offset: 0x0D8 WDT clock divider (R/W)                    */
         uint32_t RESERVED8[1];              
    __IO uint32_t CLKOUTCLKSEL;           /*!< Offset: 0x0E0 CLKOUT clock source select (R/W)           */
    __IO uint32_t CLKOUTUEN;              /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W)    */
    __IO uint32_t CLKOUTDIV;              /*!< Offset: 0x0E8 CLKOUT clock divider (R/W)                 */
         uint32_t RESERVED9[5];

    __IO uint32_t PIOPORCAP0;             /*!< Offset: 0x100 POR captured PIO status 0 (R/ )            */
    __IO uint32_t PIOPORCAP1;             /*!< Offset: 0x104 POR captured PIO status 1 (R/ )            */
         uint32_t RESERVED10[18];

    __IO uint32_t BODCTRL;                /*!< Offset: 0x150 BOD control (R/W)                          */
         uint32_t RESERVED11[1];
    __IO uint32_t SYSTCKCAL;              /*!< Offset: 0x158 System tick counter calibration (R/W)      */
         uint32_t RESERVED12;
    __IO uint32_t MAINREGVOUT0CFG;        /*!< Offset: 0x160 Main Regulator Voltage 0 Configuration     */
    __IO uint32_t MAINREGVOUT1CFG;        /*!< Offset: 0x164 Main Regulator Voltage 1 Configuration     */
         uint32_t RESERVED13[38];

    __IO uint32_t STARTAPRP0;             /*!< Offset: 0x200 Start logic edge control Register 0 (R/W)  */
    __IO uint32_t STARTERP0;              /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
    __IO uint32_t STARTRSRP0CLR;          /*!< Offset: 0x208 Start logic reset Register 0  ( /W)        */
    __IO uint32_t STARTSRP0;              /*!< Offset: 0x20C Start logic status Register 0 (R/W)        */
         uint32_t RESERVED14[8];

    __IO uint32_t PDSLEEPCFG;             /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
    __IO uint32_t PDAWAKECFG;             /*!< Offset: 0x234 Power-down states after wake-up (R/W)      */
    __IO uint32_t PDRUNCFG;               /*!< Offset: 0x238 Power-down configuration Register (R/W)    */
         uint32_t RESERVED15[101];
    __O  uint32_t VOUTCFGPROT;            /*!< Offset: 0x3D0 Voltage Output Configuration Protection    */
                                          /* Register (W)                                               */
         uint32_t RESERVED16[8];
    __I  uint32_t DEVICE_ID;              /*!< Offset: 0x3F4 Device ID (R/ )                            */
} LPC_SYSCON_TypeDef;
/*
 *  end of group LPC11xx_SYSCON
 *  @}
 */

/*********************************************************************************************************
  Pin Connect Block (IOCON)
*********************************************************************************************************/
/*
 *  @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block 
 *  @{
 */
typedef struct
{
    __IO uint32_t PIO2_6;       /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W)               */
         uint32_t RESERVED0[1];
    __IO uint32_t PIO2_0;       /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W)     */