xsusb.h

这是一个USB的驱动程序

/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:  		xsusb.h
**
**  PURPOSE:   		This files contains the definitions for UDC 
**					(USB Device controller)
**
**  LAST MODIFIED:  1/25/2001
**
******************************************************************************/

#ifndef _xsusb_h
#define _xsusb_h

#include "XsDmaApi.h"

/*
************************************************************************************
*							CONSTANTS 
************************************************************************************
*/

#ifdef UDC_GLOBALS
#define EXTRN
#else
#define EXTRN extern
#endif

// Masks for UDC Registers

// USB Control Register (UDCCR)
#define UDC_UDCCR_UDE					( 0x1 << 0 )	// UDC enabled
#define UDC_UDCCR_UDA					( 0x1 << 1 )	// READ-ONLY: udc is active
#define UDC_UDCCR_RSM					( 0x1 << 2 )	// Forces the usb out of suspend state
#define UDC_UDCCR_RESIR					( 0x1 << 3 )	// UDC received resume signalling from host
#define UDC_UDCCR_SUSIR					( 0x1 << 4 )	// UDC received	suspend signalling from host
#define UDC_UDCCR_SRM					( 0x1 << 5 )	// Suspend/Resume interrupt disabled
#define UDC_UDCCR_RSTIR					( 0x1 << 6 )	// Set when the host issues a UDC reset
#define UDC_UDCCR_REM					( 0x1 << 7 )	// Reset interrupt disabled

// UDC Endpoint 0 Control/Status Register (UDCCS0)
#define UDC_UDCCS0_OPR					( 0x1 << 0 )	// OUT packet to endpoint zero received
#define UDC_UDCCS0_IPR					( 0x1 << 1 )	// Packet has been written to endpoint zero FIFO
#define UDC_UDCCS0_FTF					( 0x1 << 2 )	// Flush the Tx FIFO
#define UDC_UDCCS0_SST					( 0x1 << 4 )	// UDC sent stall handshake
#define UDC_UDCCS0_FST					( 0x1 << 5 )	// Force the UDC to issue a stall handshake
#define UDC_UDCCS0_RNE					( 0x1 << 6 )	// There is unread data in the Rx FIFO
#define UDC_UDCCS0_SA					( 0x1 << 7 )	// Current packet in FIFO is part of UDC setup command

// UDC IN Endpoint Control/Status Register (UDCCS_IN)
#define UDC_UDCCS_TFS_IN				( 0x1 << 0 )	// Tx FIFO has room for at least one packet
#define UDC_UDCCS_TPC_IN				( 0x1 << 1 )	// Packet sent and err/status bits valid
#define UDC_UDCCS_TUR_IN				( 0x1 << 3 )	// Tx FIFO experienced underrun
#define UDC_UDCCS_SST_IN				( 0x1 << 4 )	// Write 1 to clear.  Stall was sent
#define UDC_UDCCS_FST_IN				( 0x1 << 5 )	// Issue stall handshake
#define UDC_UDCCS_TSP_IN				( 0X1 << 7 )	// Short packet ready for transmission

// UDC OUT Endpoint Control/Status Register (UDCCS_OUT)
#define UDC_UDCCS_RFS_OUT				( 0x1 << 0 )	// Rx FIFO has 1 or more packets
#define UDC_UDCCS_RPC_OUT				( 0x1 << 1 )	// Rx packet received and err/stats valid
#define UDC_UDCCS_DME_OUT				( 0x1 << 3 )	// DMA Enable
#define UDC_UDCCS_SST_OUT				( 0x1 << 4 )	// Stall handshake was sent
#define UDC_UDCCS_FST_OUT				( 0x1 << 5 )	// Issue stall handshake to OUT tokens
#define UDC_UDCCS_RNE_OUT				( 0x1 << 6 )	// Receive FIFO is not empty
#define UDC_UDCCS_RSP_OUT				( 0x1 << 7 )	// Short packet ready for reading

// UDC Interrupt Control Register 0 (UICR0)
#define UDC_UICR0_IM0					( 0x1 << 0 )	// Endpoint 0 interrupt disabled
#define UDC_UICR0_IM1					( 0x1 << 1 )	// Endpoint 1 Tx interrupt disabled
#define UDC_UICR0_IM2					( 0x1 << 2 )	// Endpoint 2 Rx interrupt disabled
#define UDC_UICR0_IM3					( 0x1 << 3 )	// Endpoint 3 Tx interrupt disabled
#define UDC_UICR0_IM4					( 0x1 << 4 )	// Endpoint 4 Rx interrupt disabled
#define UDC_UICR0_IM5					( 0x1 << 5 )	// Endpoint 5 Tx interrupt disabled
#define UDC_UICR0_IM6					( 0x1 << 6 )	// Endpoint 6 Tx interrupt disabled
#define UDC_UICR0_IM7					( 0x1 << 7 )	// Endpoint 7 Rx interrupt disabled

// UDC Interrupt Control Register 1 (UICR1)
#define UDC_UICR1_IM8					( 0x1 << 0 )	// Endpoint 8 Tx interrupt disabled
#define UDC_UICR1_IM9					( 0x1 << 1 )	// Endpoint 9 Rx interrupt disabled
#define UDC_UICR1_IM10					( 0x1 << 2 )	// Endpoint 10 Rx interrupt disabled
#define UDC_UICR1_IM11					( 0x1 << 3 )	// Endpoint 11 Tx interrupt disabled
#define UDC_UICR1_IM12					( 0x1 << 4 )	// Endpoint 12 Rx interrupt disabled
#define UDC_UICR1_IM13					( 0x1 << 5 )	// Endpoint 13 Tx interrupt disabled
#define UDC_UICR1_IM14					( 0x1 << 6 )	// Endpoint 14 Rx interrupt disabled
#define UDC_UICR1_IM15					( 0x1 << 7 )	// Endpoint 15 Rx interrupt disabled

// UDC Status/Interrupt Register 0 (UISR0)
#define UDC_UISR0_IR0					( 0x1 << 0 )	// Endpoint 0 needs service
#define UDC_UISR0_IR1					( 0x1 << 0 )	// Endpoint 1 needs service
#define UDC_UISR0_IR2					( 0x1 << 0 )	// Endpoint 2 needs service
#define UDC_UISR0_IR3					( 0x1 << 0 )	// Endpoint 3 needs service
#define UDC_UISR0_IR4					( 0x1 << 0 )	// Endpoint 4 needs service
#define UDC_UISR0_IR5					( 0x1 << 0 )	// Endpoint 5 needs service
#define UDC_UISR0_IR6					( 0x1 << 0 )	// Endpoint 6 needs service
#define UDC_UISR0_IR7					( 0x1 << 0 )	// Endpoint 7 needs service

// UDC Status/Interrupt Register 1 (UISR1)
#define UDC_UISR1_IR8					( 0x1 << 0 )	// Endpoint 8 needs service
#define UDC_UISR1_IR9					( 0x1 << 0 )	// Endpoint 9 needs service
#define UDC_UISR1_IR10					( 0x1 << 0 )	// Endpoint 10 needs service
#define UDC_UISR1_IR11					( 0x1 << 0 )	// Endpoint 11 needs service
#define UDC_UISR1_IR12					( 0x1 << 0 )	// Endpoint 12 needs service
#define UDC_UISR1_IR13					( 0x1 << 0 )	// Endpoint 13 needs service
#define UDC_UISR1_IR14					( 0x1 << 0 )	// Endpoint 14 needs service
#define UDC_UISR1_IR15					( 0x1 << 0 )	// Endpoint 15 needs service

// UDC Frame Number High Register (UFNHR)
#define UDC_UFNHR_FNMSB_SHIFT			0
#define UDC_UFNHR_FNMSB_MASK			( 0x3 << UDC_UFNHR_FNMSB_SHIFT )
                                                        // Used to read the 3 most significant bits of the
                                                        // 11-bit frame number	associated with last SOF
#define UDC_UFNHR_SIM					( 0x1 << 6 )	// SOF(start of frame) interrupt disabled
#define UDC_UFNHR_SIR					( 0x1 << 7 )	// SOF(start of frame) interrupt received												


// UDC Frame Number Low Register (UFNLR)
#define UDC_UFNLR_FNMSB_SHIFT			0
#define UDC_UFNLR_FNMSB_MASK			( 0xff << UDC_UFNLR_FNMSB_SHIFT )
                                                        // Used to read the 8 least significant bits of the
                                                        // 11-bit frame number associated with last SOF												

// UDC Byte Count Register (UBCR)
#define UDC_UBC_BYTECNT_MASK			( 0xff << 0 )	// Used to read the number of bytes
                                                        // remaining in the input buffer of
                                                        // any Endpoint


// UDC Endpoint Data Register (UDDR)

/*  The Endpoint FIFOs are composed of 32 bit words of which only the lower 8 bits are used.
    Use this mask to ensure that FIFO reads and writes are not affected by the unused bits 8-31 */
#define UDC_UDDR_RW_MASK				( 0xff << 0 )	// Used to read bottom of Endpoint 0 data  
                                                        // currently being loaded.  Also used to
                                                        // mask data to be written to top of
                                                        // Endpoint 0 data


#define UDC_REGISTERS_BASE				(0x40600000)

#define UDC_ENABLE_ALL_INT				( 0x0  )    	// Used to enable all int for EP0-7 and EP8-15
#define UDC_DISABLE_ALL_INT				( 0xff )        // Used to disable all int for EP0-7 and EP8-15
#define UDC_DMA_ENABLED					( 0x1 )			// Used to enable DMA transfer for Endpoint 
#define UDC_NO_DMA						( 0x0 )			// Used to disable DMA transfer for Endpoint 
#define UDC_DME_SET						( 0x1 )	
#define UDC_INT_MASKED					( 0x1 )
#define UDC_CONFIG1_LENGTH              32
#define UDC_CONFIG2_LENGTH              32
#define UDC_CONFIG3_LENGTH              25
#define UDC_CONFIG_TOTAL                (UDC_CONFIG1_LENGTH + UDC_CONFIG2_LENGTH + UDC_CONFIG3_LENGTH)
#define BULK_IN_LENGTH					64
#define BULK_OUT_LENGTH					64
#define ISO_IN_LENGTH					256
#define ISO_OUT_LENGTH					256
#define INT_IN_LENGTH					8
#define UDC_MAX_PACKET_SIZE_CTL 		16				// Length of the SETUP packet of Control transfer 
#define UDC_SETUP						0x81			// Used to identify a Setup transaction 
#define UDC_REQ_TYPE_MASK               (0x3 << 5)      // Used to identify a Request Type
#define	JUMP_TO_IDLE                    (0xfffffffe)	// Used to brake a loop in Endpoint 0 interrupt handler 
#define NUM_EP                          16
#define DMA_BUFF_SIZE_MIN               32
#define UDC_TEST_PATTERN                0xAA
#define UDC_DEBUG_TOTAL					512
#define NUM_TEST_BLOCKS                 16

// Error sub-location codes for ERR_L_XSUDC location code

#define ERR_S_XSUDC_HWSETUP        	0x01 // XsUdcHWSetup
#define ERR_S_XSUDC_INT_HANDLER     0x02 // XsUdc Register Interrupt Handler
#define ERR_S_XSUDC_ENABLE_INT      0x03 // XsUdc Enable Interrupt
#define ERR_S_XSUDC_FREE_MEM        0x04 // XsUdc error returning the memory
#define ERR_S_XSUDC_GET_MEM         0x05 // XsUdc no memory has been allocated
#define ERR_S_XSUDC_SHUT            0x06 // XsUdcHWShutdown 
#define ERR_S_XSUDC_DMA_IN          0x07 // XsUdcSetupEndpointDma
#define ERR_S_XSUDC_DMA_OUT         0x08 // XsUdcSetupEndpointDma

/*
************************************************************************************
*							DATA TYPES                
************************************************************************************
*/

// UDC Registers
typedef struct UdcRegsS {
    VUINT32 UDCCR;
    VUINT32	RESERVED[3];
    VUINT32	UDCCS0;
    VUINT32	UDCCS1;
    VUINT32	UDCCS2;
    VUINT32	UDCCS3;
    VUINT32	UDCCS4;
    VUINT32	UDCCS5;
    VUINT32	UDCCS6;
    VUINT32	UDCCS7;
    VUINT32	UDCCS8;
    VUINT32	UDCCS9;
    VUINT32	UDCCS10;
    VUINT32	UDCCS11;
    VUINT32	UDCCS12;
    VUINT32	UDCCS13;
    VUINT32	UDCCS14;
    VUINT32	UDCCS15;
    VUINT32	UICR0;
    VUINT32	UICR1;
    VUINT32	UISR0;
    VUINT32	UISR1;
    VUINT32	UFNHR;
    VUINT32	UFNLR;
    VUINT32	UBC2;
    VUINT32	UBC4;
    VUINT32	UBC7;
    VUINT32	UBC9;
    VUINT32	UBC12;
    VUINT32	UBC14;
    VUINT32	UDDR0;			//  16 bytes FIFO starts at 0x4060 0080
    VUINT32	RESERVED0[7];
    VUINT32	UDDR5;			//   8 bytes FIFO starts at 0x4060 00a0
    VUINT32	RESERVED5[7];
    VUINT32	UDDR10;		    //   8 bytes FIFO starts at 0x4060 00c0 
    VUINT32	RESERVED10[7];	
    VUINT32	UDDR15;			//   8 bytes FIFO starts at 0x4060 00e0
    VUINT32	RESERVED15[7];
    VUINT32	UDDR1;			//  64 bytes FIFO starts at 0x4060 0100