svinto_boot.h

linux平台上的开放源代码的网络摄像机程序.实现视频捕捉,传输以及云台控制等.非常具有参考价值.

/* $Id: svinto_boot.h,v 1.10 2001/10/31 14:41:27 johana Exp $ */

#define DMA_DESCR__out_priority__BITNR  5
#define DMA_DESCR__out_priority__WIDTH  1
#define DMA_DESCR__out_priority__normal 0
#define DMA_DESCR__out_priority__high   1

#define DMA_DESCR__ecp_cmd__BITNR  4
#define DMA_DESCR__ecp_cmd__WIDTH  1
#define DMA_DESCR__ecp_cmd__normal 0
#define DMA_DESCR__ecp_cmd__high   1

#define DMA_DESCR__tx_err__BITNR 4
#define DMA_DESCR__tx_err__WIDTH 1
#define DMA_DESCR__tx_err__enable 1
#define DMA_DESCR__tx_err__disable 0

#define DMA_DESCR__intr__BITNR  3
#define DMA_DESCR__intr__WIDTH  1
#define DMA_DESCR__intr__enable 1
#define DMA_DESCR__intr__disable 0

#define DMA_DESCR__wait__BITNR 2
#define DMA_DESCR__wait__WIDTH 1
#define DMA_DESCR__wait__enable 1
#define DMA_DESCR__wait__disable 0

#define DMA_DESCR__eop__BITNR 1
#define DMA_DESCR__eop__WIDTH 1
#define DMA_DESCR__eop__enable 1
#define DMA_DESCR__eop__disable 0

#define DMA_DESCR__eol__BITNR 0
#define DMA_DESCR__eol__WIDTH 1
#define DMA_DESCR__eol__enable 1
#define DMA_DESCR__eol__disable 0

#define DMA_DESCR__sw_len__BITNR 0
#define DMA_DESCR__sw_len__WIDTH 16

#define DMA_DESCR__next__BITNR 0
#define DMA_DESCR__next__WIDTH 32

#define DMA_DESCR__buf__BITNR 0
#define DMA_DESCR__buf__WIDTH 32

#define DMA_DESCR__fifo_len__BITNR 8
#define DMA_DESCR__fifo_len__WIDTH 7

#define DMA_DESCR__crc_err__BITNR 7
#define DMA_DESCR__crc_err__WIDTH 1
#define DMA_DESCR__crc_err__enable 1
#define DMA_DESCR__crc_err__disable 0

#define DMA_DESCR__align_err__BITNR 6
#define DMA_DESCR__align_err__WIDTH 1
#define DMA_DESCR__align_err__enable 1
#define DMA_DESCR__align_err__disable 0

#define DMA_DESCR__in_priority__BITNR 5
#define DMA_DESCR__in_priority__WIDTH 1
#define DMA_DESCR__in_priority__high 1
#define DMA_DESCR__in_priority__normal 0

#define DMA_DESCR__stop__BITNR 4
#define DMA_DESCR__stop__WIDTH 1

#define DMA_DESCR__rd_eop__BITNR 1
#define DMA_DESCR__rd_eop__WIDTH 1

#define DMA_DESCR__hw_len__BITNR 0
#define DMA_DESCR__hw_len__WIDTH 16

#define SET_ETHER_ADDR(a0_0,a0_1,a0_2,a0_3,a0_4,a0_5,a1_0,a1_1,a1_2,a1_3,a1_4,a1_5) \
  *R_NETWORK_SA_0 = a0_0 | (a0_1 << 8) | (a0_2 << 16) | (a0_3 << 24); \
  *R_NETWORK_SA_1 = a0_4 | (a0_5 << 8) | (a1_0 << 16) | (a1_1 << 24); \
  *R_NETWORK_SA_2 = a1_2 | (a1_3 << 8) | (a1_4 << 16) | (a1_5 << 24);

#define DWORD_ALIGN(x) ((x)&0xfffffffc)

#define CRC_LEN 4

#define TRUE  1
#define FALSE 0

#define NL 1
#define NO_NL 0

#define SERIAL   0
#define NETWORK  1
#define PARALLEL 2

#define STRING 0
#define INT    1
#define ACK    2
#define BOOT_PACKET 3
#define BOOT_CMDS   4
#define REJECT 5	//added by Andrey

#define JUMP           1
#define MEM_TEST       2
#define PACKET_INFO    3
#define SET_REGISTER   4
#define GET_REGISTER   5
#define MEM_DUMP       6
#define MEM_CLEAR      7
#define MEM_VERIFY     8
#define FLASH          9
#define PAUSE_LOOP     10

#define TIMEOUT_LIMIT ( ((6250 * 1000) / 0xffff) / 2)

#define TX_CTRL_EOP \
(IO_STATE(DMA_DESCR, intr, disable) |\
 IO_STATE(DMA_DESCR, wait, enable)  |\
 IO_STATE(DMA_DESCR, eop,  enable)  |\
 IO_STATE(DMA_DESCR, eol,  enable))
     
#define TX_CTRL \
     (IO_STATE(DMA_DESCR, intr, disable) |\
      IO_STATE(DMA_DESCR, wait, disable) |\
      IO_STATE(DMA_DESCR, eop,  disable) |\
      IO_STATE(DMA_DESCR, eol,  disable))
#include <serialdefines.h>

#ifdef CONFIG_DEBUG_PORT_NONE
/* Don't define macros we shouldn't use */
#elif defined CONFIG_DEBUG_PORT0
#define SERIAL_CTRL_W \
     ((IO_STATE(R_SERIAL0_CTRL, tr_baud,       c9600Hz) |\
       IO_STATE(R_SERIAL0_CTRL, rec_baud,      c9600Hz) |\
       IO_STATE(R_SERIAL0_CTRL, dma_err,       stop)     |\
       IO_STATE(R_SERIAL0_CTRL, rec_enable,    enable)   |\
       IO_STATE(R_SERIAL0_CTRL, rts_,          active)   |\
       IO_STATE(R_SERIAL0_CTRL, sampling,      middle)   |\
       IO_STATE(R_SERIAL0_CTRL, rec_stick_par, normal)   |\
       IO_STATE(R_SERIAL0_CTRL, rec_par,       even)     |\
       IO_STATE(R_SERIAL0_CTRL, rec_par_en,    disable)  |\
       IO_STATE(R_SERIAL0_CTRL, rec_bitnr,     rec_8bit)) >> 16)

#define SERIAL_CTRL_B \
     ((IO_FIELD(R_SERIAL0_CTRL, txd, 0)                  |\
       IO_STATE(R_SERIAL0_CTRL, tr_enable,     enable)   |\
       IO_STATE(R_SERIAL0_CTRL, auto_cts,      disabled) |\
       IO_STATE(R_SERIAL0_CTRL, stop_bits,     one_bit)  |\
       IO_STATE(R_SERIAL0_CTRL, tr_stick_par,  normal)   |\
       IO_STATE(R_SERIAL0_CTRL, tr_par,        even)     |\
       IO_STATE(R_SERIAL0_CTRL, tr_par_en,     disable)  |\
       IO_STATE(R_SERIAL0_CTRL, tr_bitnr,      tr_8bit)) >> 8)
#elif defined CONFIG_DEBUG_PORT1
#define SERIAL_CTRL_W \
     ((IO_STATE(R_SERIAL1_CTRL, tr_baud,       c9600Hz) |\
       IO_STATE(R_SERIAL1_CTRL, rec_baud,      c9600Hz) |\
       IO_STATE(R_SERIAL1_CTRL, dma_err,       stop)     |\
       IO_STATE(R_SERIAL1_CTRL, rec_enable,    enable)   |\
       IO_STATE(R_SERIAL1_CTRL, rts_,          active)   |\
       IO_STATE(R_SERIAL1_CTRL, sampling,      middle)   |\
       IO_STATE(R_SERIAL1_CTRL, rec_stick_par, normal)   |\
       IO_STATE(R_SERIAL1_CTRL, rec_par,       even)     |\
       IO_STATE(R_SERIAL1_CTRL, rec_par_en,    disable)  |\
       IO_STATE(R_SERIAL1_CTRL, rec_bitnr,     rec_8bit)) >> 16)

#define SERIAL_CTRL_B \
     ((IO_FIELD(R_SERIAL1_CTRL, txd, 0)                  |\
       IO_STATE(R_SERIAL1_CTRL, tr_enable,     enable)   |\
       IO_STATE(R_SERIAL1_CTRL, auto_cts,      disabled) |\
       IO_STATE(R_SERIAL1_CTRL, stop_bits,     one_bit)  |\
       IO_STATE(R_SERIAL1_CTRL, tr_stick_par,  normal)   |\
       IO_STATE(R_SERIAL1_CTRL, tr_par,        even)     |\
       IO_STATE(R_SERIAL1_CTRL, tr_par_en,     disable)  |\
       IO_STATE(R_SERIAL1_CTRL, tr_bitnr,      tr_8bit)) >> 8)
#elif defined CONFIG_DEBUG_PORT2
#define SERIAL_CTRL_W \
     ((IO_STATE(R_SERIAL2_CTRL, tr_baud,       c9600Hz) |\
       IO_STATE(R_SERIAL2_CTRL, rec_baud,      c9600Hz) |\
       IO_STATE(R_SERIAL2_CTRL, dma_err,       stop)     |\
       IO_STATE(R_SERIAL2_CTRL, rec_enable,    enable)   |\
       IO_STATE(R_SERIAL2_CTRL, rts_,          active)   |\
       IO_STATE(R_SERIAL2_CTRL, sampling,      middle)   |\
       IO_STATE(R_SERIAL2_CTRL, rec_stick_par, normal)   |\
       IO_STATE(R_SERIAL2_CTRL, rec_par,       even)     |\
       IO_STATE(R_SERIAL2_CTRL, rec_par_en,    disable)  |\
       IO_STATE(R_SERIAL2_CTRL, rec_bitnr,     rec_8bit)) >> 16)

#define SERIAL_CTRL_B \
     ((IO_FIELD(R_SERIAL2_CTRL, txd, 0)                  |\
       IO_STATE(R_SERIAL2_CTRL, tr_enable,     enable)   |\
       IO_STATE(R_SERIAL2_CTRL, auto_cts,      disabled) |\
       IO_STATE(R_SERIAL2_CTRL, stop_bits,     one_bit)  |\
       IO_STATE(R_SERIAL2_CTRL, tr_stick_par,  normal)   |\
       IO_STATE(R_SERIAL2_CTRL, tr_par,        even)     |\
       IO_STATE(R_SERIAL2_CTRL, tr_par_en,     disable)  |\
       IO_STATE(R_SERIAL2_CTRL, tr_bitnr,      tr_8bit)) >> 8)
#elif defined CONFIG_DEBUG_PORT3
#define SERIAL_CTRL_W \
     ((IO_STATE(R_SERIAL3_CTRL, tr_baud,       c9600Hz) |\
       IO_STATE(R_SERIAL3_CTRL, rec_baud,      c9600Hz) |\
       IO_STATE(R_SERIAL3_CTRL, dma_err,       stop)     |\
       IO_STATE(R_SERIAL3_CTRL, rec_enable,    enable)   |\
       IO_STATE(R_SERIAL3_CTRL, rts_,          active)   |\
       IO_STATE(R_SERIAL3_CTRL, sampling,      middle)   |\
       IO_STATE(R_SERIAL3_CTRL, rec_stick_par, normal)   |\
       IO_STATE(R_SERIAL3_CTRL, rec_par,       even)     |\
       IO_STATE(R_SERIAL3_CTRL, rec_par_en,    disable)  |\
       IO_STATE(R_SERIAL3_CTRL, rec_bitnr,     rec_8bit)) >> 16)

#define SERIAL_CTRL_B \
     ((IO_FIELD(R_SERIAL3_CTRL, txd, 0)                  |\
       IO_STATE(R_SERIAL3_CTRL, tr_enable,     enable)   |\
       IO_STATE(R_SERIAL3_CTRL, auto_cts,      disabled) |\
       IO_STATE(R_SERIAL3_CTRL, stop_bits,     one_bit)  |\
       IO_STATE(R_SERIAL3_CTRL, tr_stick_par,  normal)   |\
       IO_STATE(R_SERIAL3_CTRL, tr_par,        even)     |\
       IO_STATE(R_SERIAL3_CTRL, tr_par_en,     disable)  |\
       IO_STATE(R_SERIAL3_CTRL, tr_bitnr,      tr_8bit)) >> 8)
#endif     

#define R_PAR0_CONFIG_SETUP \
     (IO_STATE (R_PAR0_CONFIG, ioe,     noninv)    |\
      IO_STATE (R_PAR0_CONFIG, iseli,   noninv)    |\
      IO_STATE (R_PAR0_CONFIG, iautofd, noninv)    |\
      IO_STATE (R_PAR0_CONFIG, istrb,   noninv)    |\
      IO_STATE (R_PAR0_CONFIG, iinit,   noninv)    |\
      IO_STATE (R_PAR0_CONFIG, iperr,   noninv)    |\
      IO_STATE (R_PAR0_CONFIG, iack,    noninv)    |\
      IO_STATE (R_PAR0_CONFIG, ibusy,   noninv)    |\
      IO_STATE (R_PAR0_CONFIG, ifault,  noninv)    |\
      IO_STATE (R_PAR0_CONFIG, isel,    noninv)    |\
      IO_STATE (R_PAR0_CONFIG, dma,     disable)   |\
      IO_STATE (R_PAR0_CONFIG, rle_in,  disable)   |\
      IO_STATE (R_PAR0_CONFIG, rle_out, disable)   |\
      IO_STATE (R_PAR0_CONFIG, enable,  on)        |\
      IO_STATE (R_PAR0_CONFIG, force,   off)       |\
      IO_STATE (R_PAR0_CONFIG, ign_ack, wait)      |\
      IO_STATE (R_PAR0_CONFIG, oe_ack,  dont_wait) |\
      IO_STATE (R_PAR0_CONFIG, mode,    ecp_rev))

#ifdef CONFIG_DEBUG_PORT_NONE
#define R_GEN_CONFIG_SETUP \
     (IO_STATE (R_GEN_CONFIG, g24dir,    in)      |\
      IO_STATE (R_GEN_CONFIG, g16_20dir, in)      |\
      IO_STATE (R_GEN_CONFIG, g8_15dir,  in)      |\
      IO_STATE (R_GEN_CONFIG, g0dir,     in)      |\
      IO_STATE (R_GEN_CONFIG, dma9,      unused)  |\
      IO_STATE (R_GEN_CONFIG, dma8,      unused)  |\
      IO_STATE (R_GEN_CONFIG, dma7,      unused)  |\
      IO_STATE (R_GEN_CONFIG, dma6,      unused)  |\
      IO_STATE (R_GEN_CONFIG, dma5,      par1)  /* Unused, so par1 is ok, =0 */ |\
      IO_STATE (R_GEN_CONFIG, dma4,      par1)  /* Unused, so par1 is ok, =0 */ |\
      IO_STATE (R_GEN_CONFIG, dma3,      scsi0) /* Unused, (must not be 0) */ |\
      IO_STATE (R_GEN_CONFIG, dma2,      scsi0) /* Unused  (must not be 0) */ |\
      IO_STATE (R_GEN_CONFIG, mio_w,     disable) |\
      IO_STATE (R_GEN_CONFIG, ser3,      disable) |\
      IO_STATE (R_GEN_CONFIG, par1,      disable) |\
      IO_STATE (R_GEN_CONFIG, scsi0w,    disable) |\
      IO_STATE (R_GEN_CONFIG, scsi1,     disable) |\
      IO_STATE (R_GEN_CONFIG, mio,       disable) |\
      IO_STATE (R_GEN_CONFIG, ser2,      disable) |\
      IO_STATE (R_GEN_CONFIG, par0,      select)  |\
      IO_STATE (R_GEN_CONFIG, ata,       disable) |\
      IO_STATE (R_GEN_CONFIG, scsi0,     disable))
#elif defined CONFIG_DEBUG_PORT0
#define R_GEN_CONFIG_SETUP \
     (IO_STATE (R_GEN_CONFIG, g24dir,    in)      |\
      IO_STATE (R_GEN_CONFIG, g16_20dir, in)      |\
      IO_STATE (R_GEN_CONFIG, g8_15dir,  in)      |\
      IO_STATE (R_GEN_CONFIG, g0dir,     in)      |\
      IO_STATE (R_GEN_CONFIG, dma9,      unused)  |\
      IO_STATE (R_GEN_CONFIG, dma8,      unused)  |\
      IO_STATE (R_GEN_CONFIG, dma7,      unused)  |\
      IO_STATE (R_GEN_CONFIG, dma6,      unused)  |\
      IO_STATE (R_GEN_CONFIG, dma5,      par1)  /* Unused, so par1 is ok, =0 */ |\
      IO_STATE (R_GEN_CONFIG, dma4,      par1)  /* Unused, so par1 is ok, =0 */ |\
      IO_STATE (R_GEN_CONFIG, dma3,      scsi0) /* Unused, (must not be 0) */ |\
      IO_STATE (R_GEN_CONFIG, dma2,      scsi0) /* Unused  (must not be 0) */ |\
      IO_STATE (R_GEN_CONFIG, mio_w,     disable) |\
      IO_STATE (R_GEN_CONFIG, ser3,      disable) |\
      IO_STATE (R_GEN_CONFIG, par1,      disable) |\
      IO_STATE (R_GEN_CONFIG, scsi0w,    disable) |\
      IO_STATE (R_GEN_CONFIG, scsi1,     disable) |\
      IO_STATE (R_GEN_CONFIG, mio,       disable) |\
      IO_STATE (R_GEN_CONFIG, ser2,      disable) |\
      IO_STATE (R_GEN_CONFIG, par0,      select)  |\