📄 61ic工程师社区-tms320lf2407的头文件和一些c语言例程f2407regs_h.htm
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align=top><B>以文本方式查看主题</B><BR><BR>- <B>61IC工程师社区</B> (http://www.61ic.com/bbs/index.asp)<BR>-- <B>[C2000]</B> (http://www.61ic.com/bbs/list.asp?boardid=7)<BR>---- <B>TMS320LF2407的头文件和一些c语言例程F2407REGS.H</B> (http://www.61ic.com/bbs/dispbbs.asp?boardid=7&id=3119)<BR>
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<TD vAlign=center
align=top>-- 作者：info<BR>-- 发布时间：2005-1-4
11:14:36<BR><BR>-- TMS320LF2407的头文件和一些c语言例程F2407REGS.H<BR>;
Originator: Texas Instruments<BR>; Description: F240
Header file containing all peripheral register <BR>;
declarations as well as other useful definitions.<BR>; Last
Updated: 27 May 1997<BR>;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>;
On Chip Periperal Register Definitions (All registers mapped into data
<BR>; space unless otherwise noted)<BR>;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>;全局变量寄存器和CPU中断寄存器<BR>;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>IMR .set
0004h ;中断屏蔽寄存器<BR>GREG .set
0005h ;全局变量定位寄存器<BR>IFR .set
0006h ;中断标志寄存器<BR>;System Registers<BR>;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>PIRQR0 .set
07010h<BR>PIRQR1 .set 07011h<BR>PIRQR2 .set
07012h<BR>PIACKR0 .set 07014h<BR>PIACKR1 .set
07015h<BR>PIACKR2 .set 07016h<BR>SCSR1 .set
07018h ;系统模块控制寄存器1<BR>SCSR2 .set
07019h ;系统模块控制寄存器2<BR>DINR .set
0701Ch ;系统模块状态寄存器<BR>PIVR .set
0701Eh ;系统中断矢量寄存器<BR>;WD 程序监视控制寄存器<BR>;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>WDCNTR
.set 07023h ;WD 计数器寄存器<BR>WDKEY .set
07025h ;WDKey 寄存器<BR>WDCR .set 07029h ;WD
控制寄存器<BR>;串行外围接口 (SPI) 寄存器<BR>;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>SPICCR .set
07040h ;SPI 配置控制寄存器<BR>SPICTL .set
07041h ;SPI 操作控制寄存器<BR>SPISTS .set
07042h ;SPI 状态寄存器<BR>SPIBRR .set
07044h ;SPI 波特率寄存器<BR>SPIEMU .set
07046h ;SPI 仿真缓冲寄存器<BR>SPIRXBUF .set
07047h ;SPI 串行输入缓冲寄存器<BR>SPITXBUF .set
07048h ;SPI 串行输入缓冲寄存器<BR>SPIDAT .set
07049h ;SPI 串行数据寄存器<BR>SPIPRI .set
0704Fh ;SPI 中断优先级控制寄存器<BR>;串行通讯接口 (SCI) 寄存器<BR>;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>SCICCR .set
07050h ;SCI 通讯控制寄存器<BR>SCICTL1 .set
07051h ;SCI 控制寄存器 1<BR>SCIHBAUD .set 07052h ;SCI
波特率寄存器高位<BR>SCILBAUD .set 07053h ;SCI
波特率寄存器低位<BR>SCICTL2 .set 07054h ;SCI 控制寄存器
2<BR>SCIRXST .set 07055h ;SCI 接受状态寄存器<BR>SCIRXEMU
.set 07056h ;SCI 仿真数据缓冲寄存器<BR>SCIRXBUF .set
07057h ;SCI 接受数据缓冲寄存器<BR>SCITXBUF .set 07059h ;SCI
发送数据缓冲寄存器<BR>SCIPRI .set 0705Fh ;SCI
中断优先级控制寄存器<BR>;外部中断寄存器<BR>;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>XINT1CR .set
07070h ;中断 1 控制寄存器<BR>XINT2CR .set
07071h ;中断 2 控制寄存器<BR>;数据 I/O 控制寄存器<BR>;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>MCRA .set
07090h ;Output Control Reg A<BR>MCRB .set
07092h ;Output Control Reg B<BR>MCRC .set
07094h ;Output Control Reg C<BR>PEDATDIR .set
07095h ;I/O port E Data & Direction reg.<BR>PFDATDIR .set
07096h ;I/O port F Data & Direction reg.<BR>PADATDIR .set
07098h ;I/O port A Data & Direction reg.<BR>PBDATDIR .set
0709Ah ;I/O port B Data & Direction reg.<BR>PCDATDIR .set
0709Ch ;I/O port C Data & Direction reg.<BR>PDDATDIR .set
0709Eh ;I/O port D Data & Direction reg.<BR>;模数转换(ADC)
寄存器<BR>;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>ADCCTRL1
.set 070A0h ;ADC 控制寄存器 1<BR>ADCCTRL2 .set
070A1h ;ADC 控制寄存器 2<BR>MAXCONV .set
070A2h <BR>CHSELSEQ1 .set 070A3h <BR>CHSELSEQ2 .set
070A4h <BR>CHSELSEQ3 .set 070A5h <BR>CHSELSEQ4 .set
070A6h <BR>AUTO_SEQ_SR .set
070A7h <BR>RESULT0 .set
070A8h ;A/D转换结果寄存器0<BR>RESULT1 .set
070A9h ;A/D转换结果寄存器1<BR>RESULT2 .set
070AAh ;A/D转换结果寄存器2<BR>RESULT3 .set
070ABh ;A/D转换结果寄存器3<BR>RESULT4 .set
070ACh ;A/D转换结果寄存器4<BR>RESULT5 .set
070ADh ;A/D转换结果寄存器5<BR>RESULT6 .set
070AEh ;A/D转换结果寄存器6<BR>RESULT7 .set
070AFh ;A/D转换结果寄存器7<BR>RESULT8 .set
070B0h ;A/D转换结果寄存器8<BR>RESULT9 .set
070B1h ;A/D转换结果寄存器9<BR>RESULT10 .set
070B2h ;A/D转换结果寄存器10<BR>RESULT11 .set
070B3h ;A/D转换结果寄存器11<BR>RESULT12 .set
070B4h ;A/D转换结果寄存器12<BR>RESULT13 .set
070B5h ;A/D转换结果寄存器13<BR>RESULT14 .set
070B6h ;A/D转换结果寄存器14<BR>RESULT15 .set
070B7h ;A/D转换结果寄存器15<BR>CALIBRATION .set
070B8h <BR>;CAN 配置控制寄存器<BR>;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>MDER .set
07100h <BR>TCR .set
07101h <BR>RCR .set
07102h <BR>MCR .set
07103h <BR>BCR2 .set
07104h <BR>BCR1 .set
07105h <BR>ESR .set
07106h <BR>GSR .set
07107h <BR>CEC .set
07108h <BR>CAN_IFR .set 07109h <BR>CAN_IMR .set 0710Ah <BR>LAM0_H .set
0710Bh <BR>LAM0_L .set
0710Ch <BR>LAM1_H .set
0710Dh <BR>LAM1_L .set
0710Eh <BR>;邮包#0<BR>MSGID0L .set
07200h <BR>MSGID0H .set
07201h <BR>MSGCTRL0 .set
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