shift16.tan.rpt

多路移位寄存器dsasg asgagvgdafgadtgertgdafgdafgda

; N/A   ; None         ; 4.683 ns   ; pi[0]  ; tmp[0]  ; clk      ;
; N/A   ; None         ; 4.637 ns   ; pi[1]  ; tmp[1]  ; clk      ;
; N/A   ; None         ; 4.369 ns   ; pi[3]  ; tmp[3]  ; clk      ;
+-------+--------------+------------+--------+---------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+---------+--------+------------+
; Slack ; Required tco ; Actual tco ; From    ; To     ; From Clock ;
+-------+--------------+------------+---------+--------+------------+
; N/A   ; None         ; 8.100 ns   ; tmp[1]  ; po[1]  ; clk        ;
; N/A   ; None         ; 8.094 ns   ; tmp[6]  ; po[6]  ; clk        ;
; N/A   ; None         ; 8.036 ns   ; tmp[15] ; so     ; clk        ;
; N/A   ; None         ; 8.036 ns   ; tmp[15] ; po[15] ; clk        ;
; N/A   ; None         ; 7.946 ns   ; tmp[12] ; po[12] ; clk        ;
; N/A   ; None         ; 7.901 ns   ; tmp[14] ; po[14] ; clk        ;
; N/A   ; None         ; 7.747 ns   ; tmp[8]  ; po[8]  ; clk        ;
; N/A   ; None         ; 7.645 ns   ; tmp[3]  ; po[3]  ; clk        ;
; N/A   ; None         ; 7.599 ns   ; tmp[7]  ; po[7]  ; clk        ;
; N/A   ; None         ; 7.542 ns   ; tmp[13] ; po[13] ; clk        ;
; N/A   ; None         ; 7.443 ns   ; tmp[11] ; po[11] ; clk        ;
; N/A   ; None         ; 7.436 ns   ; tmp[4]  ; po[4]  ; clk        ;
; N/A   ; None         ; 7.428 ns   ; tmp[0]  ; po[0]  ; clk        ;
; N/A   ; None         ; 7.323 ns   ; tmp[5]  ; po[5]  ; clk        ;
; N/A   ; None         ; 7.273 ns   ; tmp[2]  ; po[2]  ; clk        ;
; N/A   ; None         ; 6.992 ns   ; tmp[10] ; po[10] ; clk        ;
; N/A   ; None         ; 6.959 ns   ; tmp[9]  ; po[9]  ; clk        ;
+-------+--------------+------------+---------+--------+------------+


+-----------------------------------------------------------------------+
; th                                                                    ;
+---------------+-------------+-----------+--------+---------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To      ; To Clock ;
+---------------+-------------+-----------+--------+---------+----------+
; N/A           ; None        ; -4.317 ns ; pi[3]  ; tmp[3]  ; clk      ;
; N/A           ; None        ; -4.585 ns ; pi[1]  ; tmp[1]  ; clk      ;
; N/A           ; None        ; -4.631 ns ; pi[0]  ; tmp[0]  ; clk      ;
; N/A           ; None        ; -4.779 ns ; ldr    ; tmp[4]  ; clk      ;
; N/A           ; None        ; -4.788 ns ; ldr    ; tmp[9]  ; clk      ;
; N/A           ; None        ; -4.792 ns ; ldr    ; tmp[1]  ; clk      ;
; N/A           ; None        ; -4.799 ns ; ldr    ; tmp[0]  ; clk      ;
; N/A           ; None        ; -4.800 ns ; ldr    ; tmp[2]  ; clk      ;
; N/A           ; None        ; -4.801 ns ; ldr    ; tmp[8]  ; clk      ;
; N/A           ; None        ; -4.871 ns ; ldr    ; tmp[3]  ; clk      ;
; N/A           ; None        ; -4.881 ns ; ldr    ; tmp[5]  ; clk      ;
; N/A           ; None        ; -4.883 ns ; ldr    ; tmp[6]  ; clk      ;
; N/A           ; None        ; -4.888 ns ; ldr    ; tmp[7]  ; clk      ;
; N/A           ; None        ; -4.936 ns ; pi[10] ; tmp[10] ; clk      ;
; N/A           ; None        ; -4.963 ns ; si     ; tmp[0]  ; clk      ;
; N/A           ; None        ; -4.969 ns ; pi[9]  ; tmp[9]  ; clk      ;
; N/A           ; None        ; -5.074 ns ; pi[15] ; tmp[15] ; clk      ;
; N/A           ; None        ; -5.077 ns ; ldr    ; tmp[14] ; clk      ;
; N/A           ; None        ; -5.079 ns ; ldr    ; tmp[11] ; clk      ;
; N/A           ; None        ; -5.081 ns ; ldr    ; tmp[10] ; clk      ;
; N/A           ; None        ; -5.158 ns ; ldr    ; tmp[13] ; clk      ;
; N/A           ; None        ; -5.160 ns ; ldr    ; tmp[15] ; clk      ;
; N/A           ; None        ; -5.171 ns ; ldr    ; tmp[12] ; clk      ;
; N/A           ; None        ; -5.177 ns ; pi[14] ; tmp[14] ; clk      ;
; N/A           ; None        ; -5.191 ns ; pi[11] ; tmp[11] ; clk      ;
; N/A           ; None        ; -5.203 ns ; pi[12] ; tmp[12] ; clk      ;
; N/A           ; None        ; -5.235 ns ; pi[4]  ; tmp[4]  ; clk      ;
; N/A           ; None        ; -5.236 ns ; pi[7]  ; tmp[7]  ; clk      ;
; N/A           ; None        ; -5.241 ns ; pi[8]  ; tmp[8]  ; clk      ;
; N/A           ; None        ; -5.261 ns ; pi[13] ; tmp[13] ; clk      ;
; N/A           ; None        ; -5.300 ns ; pi[5]  ; tmp[5]  ; clk      ;
; N/A           ; None        ; -5.404 ns ; pi[2]  ; tmp[2]  ; clk      ;
; N/A           ; None        ; -5.707 ns ; pi[6]  ; tmp[6]  ; clk      ;
+---------------+-------------+-----------+--------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Jul 30 19:01:20 2005
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shift16 -c shift16 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "tmp[9]" and destination register "tmp[10]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.327 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y5_N7; Fanout = 2; REG Node = 'tmp[9]'
            Info: 2: + IC(0.720 ns) + CELL(0.607 ns) = 1.327 ns; Loc. = LC_X16_Y5_N4; Fanout = 2; REG Node = 'tmp[10]'
            Info: Total cell delay = 0.607 ns ( 45.74 % )
            Info: Total interconnect delay = 0.720 ns ( 54.26 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.903 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'
                Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X16_Y5_N4; Fanout = 2; REG Node = 'tmp[10]'
                Info: Total cell delay = 2.180 ns ( 75.09 % )
                Info: Total interconnect delay = 0.723 ns ( 24.91 % )
            Info: - Longest clock path from clock "clk" to source register is 2.903 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'
                Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X15_Y5_N7; Fanout = 2; REG Node = 'tmp[9]'
                Info: Total cell delay = 2.180 ns ( 75.09 % )
                Info: Total interconnect delay = 0.723 ns ( 24.91 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "tmp[6]" (data pin = "pi[6]", clock pin = "clk") is 5.759 ns
    Info: + Longest pin to register delay is 8.625 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_65; Fanout = 1; PIN Node = 'pi[6]'
        Info: 2: + IC(6.412 ns) + CELL(0.738 ns) = 8.625 ns; Loc. = LC_X15_Y5_N4; Fanout = 2; REG Node = 'tmp[6]'
        Info: Total cell delay = 2.213 ns ( 25.66 % )
        Info: Total interconnect delay = 6.412 ns ( 74.34 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X15_Y5_N4; Fanout = 2; REG Node = 'tmp[6]'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
Info: tco from clock "clk" to destination pin "po[1]" through register "tmp[1]" is 8.100 ns
    Info: + Longest clock path from clock "clk" to source register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X15_Y5_N8; Fanout = 2; REG Node = 'tmp[1]'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.973 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y5_N8; Fanout = 2; REG Node = 'tmp[1]'
        Info: 2: + IC(2.849 ns) + CELL(2.124 ns) = 4.973 ns; Loc. = PIN_48; Fanout = 0; PIN Node = 'po[1]'
        Info: Total cell delay = 2.124 ns ( 42.71 % )
        Info: Total interconnect delay = 2.849 ns ( 57.29 % )
Info: th for register "tmp[3]" (data pin = "pi[3]", clock pin = "clk") is -4.317 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X15_Y5_N6; Fanout = 2; REG Node = 'tmp[3]'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.235 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_88; Fanout = 1; PIN Node = 'pi[3]'
        Info: 2: + IC(5.451 ns) + CELL(0.309 ns) = 7.235 ns; Loc. = LC_X15_Y5_N6; Fanout = 2; REG Node = 'tmp[3]'
        Info: Total cell delay = 1.784 ns ( 24.66 % )
        Info: Total interconnect delay = 5.451 ns ( 75.34 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Jul 30 19:01:21 2005
    Info: Elapsed time: 00:00:01