📄 l1_const.h
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#define D_ATTMAX 53L
#define D_SM -892L
#define D_B 208L
#define D_SD_MIN_THR_TCHFS 15L //(24L *C_POND_RED)
#define D_MA_MIN_THR_TCHFS 738L //(1200L *C_POND_RED)
#define D_MD_MAX_THR_TCHFS 1700L //(2000L *C_POND_RED)
#define D_MD1_MAX_THR_TCHFS 99L //(160L *C_POND_RED)
#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
// Frequency burst definitions
#define D_FB_MARGIN_BEG 24
#define D_FB_MARGIN_END 22
// V42bis definitions
#define D_V42B_SWITCH_HYST 16L
#define D_V42B_SWITCH_MIN 64L
#define D_V42B_SWITCH_MAX 250L
#define D_V42B_RESET_DELAY 10L
// Latencies definitions
#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
// C.f. BUG1404
#define D_LAT_MCU_BRIDGE 0x000FL
#else
#define D_LAT_MCU_BRIDGE 0x0009L
#endif
#define D_LAT_MCU_HOM2SAM 0x000CL
#define D_LAT_MCU_BEF_FAST_ACCESS 0x0005L
#define D_LAT_DSP_AFTER_SAM 0x0004L
// Background Task in GSM mode: Initialization.
#define D_GSM_BGD_MGT 0L
#if (CHIPSET == 4)
#define D_MISC_CONFIG 0L
#elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
#define D_MISC_CONFIG 1L
#else
#define D_MISC_CONFIG 0L
#endif
#endif
// Hall Rate vocoder and ched definitions.
#define D_SD_MIN_THR_TCHHS 37L
#define D_MA_MIN_THR_TCHHS 344L
#define D_MD_MAX_THR_TCHHS 2175L
#define D_MD1_MAX_THR_TCHHS 138L
#define D_SD_AV_THR_TCHHS 1845L
#define D_WED_FIL_TC 0x7c00L
#define D_WED_FIL_INI 4650L
#define D_X_MIN 15L
#define D_X_MAX 23L
#define D_Y_MIN 703L
#define D_Y_MAX 2460L
#define D_SLOPE 135L
#define D_WED_DIFF_THRESHOLD 406L
#define D_MABFI_MIN_THR_TCHHS 5320L
#define D_LDT_HR -5
#define D_MACCTRESH_HR 6500
#define D_MACCTRESH1_HR 6500
#define D_GU_HR 2620
#define D_GO_HR 3700
#define D_B_HR 182
#define D_SM_HR -1608
#define D_ATTMAX_HR 53
// Enhanced Full Rate vocoder and ched definitions.
#define C_MLDT_EFR -4
#define C_MACCTHRESH_EFR 8000
#define C_MACCTHRESH1_EFR 8000
#define C_GU_EFR 4522
#define C_GO_EFR 6500
#define C_B_EFR 174
#define C_SM_EFR -878
#define C_ATTMAX_EFR 53
#define D_SD_MIN_THR_TCHEFS 15L //(24L *C_POND_RED)
#define D_MA_MIN_THR_TCHEFS 738L //(1200L *C_POND_RED)
#define D_MD_MAX_THR_TCHEFS 1230L //(2000L *C_POND_RED)
#define D_MD1_MAX_THR_TCHEFS 99L //(160L *C_POND_RED)
// Integrated Data Services definitions.
#define D_MAX_OVSPD_UL 8
// Detect frames containing 90% of 1s as synchro frames
#define D_SYNC_THRES 0x3f50
// IDLE frames are only frames with 100 % of 1s
#define D_IDLE_THRES 0x4000
#define D_M1_THRES 5
#define D_MAX_OVSP_DL 8
// d_ra_act: bit field definition
#define B_F48BLK 5
// Mask for b_itc information (d_ra_conf)
#define CE_MASK 0x04
#define D_FACCH_THR 0
#define D_DSP_TEST 0
#define D_VERSION_NUMBER 0
#define D_TI_VERSION 0
/*------------------------------------------------------------------------------*/
/* */
/* DEFINITIONS FOR DSP <-> MCU COMMUNICATION. */
/* ++++++++++++++++++++++++++++++++++++++++++ */
/* */
/*------------------------------------------------------------------------------*/
// COMMUNICATION Interrupt definition
//------------------------------------
#define ALL_16BIT 0xffffL
#define B_GSM_PAGE (TRUE_L << 0)
#define B_GSM_TASK (TRUE_L << 1)
#define B_MISC_PAGE (TRUE_L << 2)
#define B_MISC_TASK (TRUE_L << 3)
#define B_GSM_PAGE_MASK (ALL_16BIT ^ B_GSM_PAGE)
#define B_GSM_TASK_MASK (ALL_16BIT ^ B_GSM_TASK)
#define B_MISC_PAGE_MASK (ALL_16BIT ^ B_MISC_PAGE)
#define B_MISC_TASK_MASK (ALL_16BIT ^ B_MISC_TASK)
// Common definition
//----------------------------------
// Index to *_DEMOD* arrays.
#define D_TOA 0 // Time Of Arrival.
#define D_PM 1 // Power Measurement.
#define D_ANGLE 2 // Angle (AFC correction)
#define D_SNR 3 // Signal / Noise Ratio.
// Bit name/position definitions.
#define B_FIRE0 5 // Fire result bit 0. (00 -> NO ERROR) (01 -> ERROR CORRECTED)
#define B_FIRE1 6 // Fire result bit 1. (10 -> ERROR) (11 -> unused)
#define B_SCH_CRC 8 // CRC result for SB decoding. (1 for ERROR).
#define B_BLUD 15 // Uplink,Downlink data block Present. (1 for PRESENT).
#define B_AF 14 // Activity bit: 1 if data block is valid.
#define B_BFI 2 // Bad Frame Indicator
#define B_UFI 0 // UNRELIABLE FRAME Indicator
#define B_ECRC 9 // Enhanced full rate CRC bit
#define B_EMPTY_BLOCK 10 // for voice memo purpose, this bit is used to determine
#if (DEBUG_DEDIC_TCH_BLOCK_STAT == 1)
#define FACCH_GOOD 10
#define FACCH_BAD 11
#endif
#if (AMR == 1)
// Place of the RX type in the AMR block header
#define RX_TYPE_SHIFT 3
#define RX_TYPE_MASK 0x0038
// Place of the vocoder type in the AMR block header
#define VOCODER_TYPE_SHIFT 0
#define VOCODER_TYPE_MASK 0x0007
// List of the possible RX type
#define SPEECH_GOOD 0
#define SPEECH_DEGRADED 1
#define ONSET 2
#define SPEECH_BAD 3
#define SID_FIRST 4
#define SID_UPDATE 5
#define SID_BAD 6
#define AMR_NO_DATA 7
#define AMR_INHIBIT 8
// List of the possible AMR channel rate
#define AMR_CHANNEL_4_75 0
#define AMR_CHANNEL_5_15 1
#define AMR_CHANNEL_5_9 2
#define AMR_CHANNEL_6_7 3
#define AMR_CHANNEL_7_4 4
#define AMR_CHANNEL_7_95 5
#define AMR_CHANNEL_10_2 6
#define AMR_CHANNEL_12_2 7
#endif
// "d_ctrl_tch" bits positions for TCH configuration.
#define B_CHAN_MODE 0
#define B_CHAN_TYPE 4
#define B_RESET_SACCH 6
#define B_VOCODER_ON 7
#define B_SYNC_TCH_UL 8
#if (AMR == 1)
#define B_SYNC_AMR 9
#else
#define B_SYNC_TCH_DL 9
#endif
#define B_STOP_TCH_UL 10
#define B_STOP_TCH_DL 11
#define B_TCH_LOOP 12
#define B_SUBCHANNEL 15
// "d_ctrl_abb" bits positions for conditionnal loading of abb registers.
#define B_RAMP 0
#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
#define B_BULRAMPDEL 3 // Note: this name is changed
#define B_BULRAMPDEL2 2 // Note: this name is changed
#define B_BULRAMPDEL_BIS 9
#define B_BULRAMPDEL2_BIS 10
#endif
#define B_AFC 4
// "d_ctrl_system" bits positions.
#define B_TSQ 0
#define B_BCCH_FREQ_IND 3
#define B_TASK_ABORT 15 // Abort RF tasks for DSP.
//****************************************************************
// POLESTAR EVABOARD 3 REGISTERS & ADRESSES DEFINITIONS
//****************************************************************
// DSP ADRESSES
//--------------------
#define DB_SIZE (4*20L) // 4 pages of 20 words...
#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
#define DB_W_PAGE_0 0xFFD00000L // DB page 0 write : 20 words long
#define DB_W_PAGE_1 0xFFD00028L // DB page 1 write : 20 words long
#define DB_R_PAGE_0 0xFFD00050L // DB page 0 read : 20 words long
#define DB_R_PAGE_1 0xFFD00078L // DB page 1 read : 20 words long
#define NDB_ADR 0xFFD001A8L // NDB start address : 268 words
#define PARAM_ADR 0xFFD00862L // PARAM start address : 57 words
#if (DSP_DEBUG_TRACE_ENABLE)
#define DB2_R_PAGE_0 0xFFD00184L
#define DB2_R_PAGE_1 0xFFD00188L
#endif
#else
#define DB_W_PAGE_0 0xFFD00000L // DB page 0 write : 20 words long
#define DB_W_PAGE_1 0xFFD00028L // DB page 1 write : 20 words long
#define DB_R_PAGE_0 0xFFD00050L // DB page 0 read : 20 words long
#define DB_R_PAGE_1 0xFFD00078L // DB page 1 read : 20 words long
#define NDB_ADR 0xFFD000a0L // NDB start address : 268 words
#define PARAM_ADR 0xFFD002b8L // PARAM start address : 57 words
#endif
//****************************************************************
// ADC reading definitions
//****************************************************************
#define ADC_READ_PERIOD (40) //30 * 4.615 = 140ms
//****************************************************************
// AGC: IL table identifier used by function Cust_get_agc_from_IL
//****************************************************************
#define MAX_ID 1
#define AV_ID 2
#define PWR_ID 3
#if TESTMODE
//****************************************************************
// Testmode: State of the continous mode
//****************************************************************
#define TM_NO_CONTINUOUS 1 // continuous mode isn't active
#define TM_START_RX_CONTINUOUS 2 // start the Rx continuous mode
#define TM_START_TX_CONTINUOUS 3 // start the Tx continuous mode
#define TM_CONTINUOUS 4 // Rx or Tx continuous mode
#endif
#if (AMR == 1)
//****************************************************************
// AMR: Position of each AMR parameters in the AMR API buffer
//****************************************************************
#define NSCB_INDEX 0
#define NSCB_SHIFT 6
#define ICMUL_INDEX 0
#define ICMUL_SHIFT 4
#define ICMDL_INDEX 0
#define ICMDL_SHIFT 1
#define ICMIUL_INDEX 0
#define ICMIUL_SHIFT 3
#define ICMIDL_INDEX 0
#define ICMIDL_SHIFT 0
#define ACSUL_INDEX 1
#define ACSUL_SHIFT 0
#define ACSDL_INDEX 1
#define ACSDL_SHIFT 8
#define THR1_INDEX 2
#define THR1_SHIFT 0
#define THR2_INDEX 2
#define THR2_SHIFT 6
#define THR3_INDEX 3
#define THR3_SHIFT 8
#define HYST1_INDEX 3
#define HYST1_SHIFT 0
#define HYST2_INDEX 3
#define HYST2_SHIFT 4
#define HYST3_INDEX 2
#define HYST3_SHIFT 12
#define NSYNC_INDEX 3
#define NSYNC_SHIFT 14
#define NSCB_MASK 0x0001
#define ICM_MASK 0x0003
#define ICMI_MASK 0x0001
#define ACS_MASK 0x00FF
#define THR_MASK 0x003F
#define HYST_MASK 0x000F
#endif
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