📄 l1_confg.h
字号:
#endif
/* d_error_status */
/*-------------------------------*/
#if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
#define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
// masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
#define DSP_DEBUG_GSM_MASK 0x0000
#define DSP_DEBUG_GPRS_MASK 0x0f3d
#endif
#elif (DSP == 35) // ROM Code GPRS AMR.
#define CLKMOD1 0x4006 // ...
#define CLKMOD2 0x4116 // ...65 Mips pll free
#define CLKSTART 0x29 // ...65 Mips
#define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
#define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
#define AEC 1 // AEC/NS not supported.
#if (OP_RIV_AUDIO == 0)
#define L1_NEW_AEC 1
#else
// Not yet available with Riviera AUDIO
#define L1_NEW_AEC 0
#endif
#if ((L1_NEW_AEC) && (!AEC))
// First undef the flag to avoid warnings at compilation time
#undef AEC
#define AEC 1
#endif
#define MAP 3
#define DSP_START 0x7000
#define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
#define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
#define ULYSSE 0
#define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
#if ((CHIPSET != 10) && (CHIPSET != 11) && (CHIPSET != 12))
#define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
// management.
#else
#define W_A_DSP_IDLE3 0
#endif
// DSP software work-around config
// bit0 - Work-around to support CRTG.
// bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
// bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
// bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
#if (ANALOG == 1) // OMEGA / NAUSICA
#define C_DSP_SW_WORK_AROUND 0x0006
#elif (ANALOG == 2) // IOTA
#define C_DSP_SW_WORK_AROUND 0x000E
#elif (ANALOG == 3) // SYREN
#define C_DSP_SW_WORK_AROUND 0x000E
#endif
/* DSP debug trace configuration */
/*-------------------------------*/
#if (MELODY_E2)
// In case of the melody E2 the DSP trace must be disable because the
// melody instrument waves are overlayed with DSP trace buffer
// DSP debug trace API buufer config
#define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
#define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
// DSP debug trace type config
// |<-------------- Features -------------->|<---------- Levels ----------->|
// [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
#define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
#if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
#define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
// Currently not supported !
#endif
#else
// DSP debug trace API buufer config
#define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
#define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
// DSP debug trace type config
// |<-------------- Features -------------->|<---------- Levels ----------->|
// [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
#define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Timer + Buffer Header + Burst.
#if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
#define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
#endif
// AMR trace
#define C_AMR_TRACE_ID 55
#endif
/* d_error_status */
/*-------------------------------*/
#if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
#define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
// masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
#define DSP_DEBUG_GSM_MASK 0x0000
#define DSP_DEBUG_GPRS_MASK 0x0f3d
#endif
#elif (DSP == 36) // ROM Code GPRS AMR.
#define CLKMOD1 0x4006 // ...
#define CLKMOD2 0x4116 // ...65 Mips pll free
#define CLKSTART 0x29 // ...65 Mips
#define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
#define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
#define AEC 1 // AEC/NS not supported.
#if (OP_RIV_AUDIO == 0)
#define L1_NEW_AEC 1
#else
// Not yet available with Riviera AUDIO
#define L1_NEW_AEC 0
#endif
#if ((L1_NEW_AEC) && (!AEC))
// First undef the flag to avoid warnings at compilation time
#undef AEC
#define AEC 1
#endif
#define MAP 3
#undef L1_AMR_NSYNC
#define L1_AMR_NSYNC 1
#define FF_L1_TCH_VOCODER_CONTROL 1
#define DSP_START 0x7000
#define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
#define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
#define ULYSSE 0
#define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
#if ((CHIPSET != 10) && (CHIPSET != 11) && (CHIPSET != 12))
#define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
// management.
#else
#define W_A_DSP_IDLE3 0
#endif
// DSP software work-around config
// bit0 - Work-around to support CRTG.
// bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
// bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
// bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
#if (ANALOG == 1) // OMEGA / NAUSICA
#define C_DSP_SW_WORK_AROUND 0x0006
#elif (ANALOG == 2) // IOTA
#define C_DSP_SW_WORK_AROUND 0x000E
#elif (ANALOG == 3) // SYREN
#define C_DSP_SW_WORK_AROUND 0x000E
#endif
/* DSP debug trace configuration */
/*-------------------------------*/
#if (MELODY_E2)
// In case of the melody E2 the DSP trace must be disable because the
// melody instrument waves are overlayed with DSP trace buffer
// DSP debug trace API buufer config
#define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
#define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
// DSP debug trace type config
// |<-------------- Features -------------->|<---------- Levels ----------->|
// [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
#define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
#if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
#define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
// Currently not supported !
#endif
#else
// DSP debug trace API buufer config
#define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
#define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
// DSP debug trace type config
// |<-------------- Features -------------->|<---------- Levels ----------->|
// [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
#define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
#if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
#define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
#endif
// AMR trace
#define C_AMR_TRACE_ID 55
#endif
/* d_error_status */
/*-------------------------------*/
#if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
#define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
// masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
#define DSP_DEBUG_GSM_MASK 0x0000
#define DSP_DEBUG_GPRS_MASK 0x0f3d
#endif
#endif // DSP
/*------------------------------------*/
/* Default value */
/*------------------------------------*/
#ifndef W_A_DSP1
#define W_A_DSP1 0
#endif
#ifndef DATA14_4
#define DATA14_4 0
#endif
#ifndef W_A_ITFORCE
#define W_A_ITFORCE 0
#endif
#ifndef W_A_DSP_IDLE3
#define W_A_DSP_IDLE3 0
#endif
#ifndef L1_NEW_AEC
#define L1_NEW_AEC 0
#endif
#ifndef DSP_DEBUG_TRACE_ENABLE
#define DSP_DEBUG_TRACE_ENABLE 0
#endif
#ifndef DEBUG_DEDIC_TCH_BLOCK_STAT
#define DEBUG_DEDIC_TCH_BLOCK_STAT 0
#endif
#ifndef D_ERROR_STATUS_TRACE_ENABLE
#define D_ERROR_STATUS_TRACE_ENABLE 0
#endif
#ifndef L1_GTT
#define L1_GTT 0
#endif
#ifndef L1_AMR_NSYNC
#define L1_AMR_NSYNC 0
#endif
#ifndef FF_L1_TCH_VOCODER_CONTROL
#define FF_L1_TCH_VOCODER_CONTROL 0
#endif
/*------------------------------------*/
/* Download */
/*------------------------------------*/
/* Possible values for the download status */
#define LEAD_READY 1
#define BLOCK_READY 2
#define PROGRAM_DONE 3
#define PAGE_SELECTION 4
/************************************/
/* Options of compilation... */
/************************************/
// Possible choice of hardware plateform.
#define GEMINI 1 // GEMINI chip (rom dsp code)
#define POLESTAR 2 // POLESTAR chip (no rom)
// Possible choice for DSP software setup.
#define NO_DWNLD 0
#define PATCH_DWNLD 1
#define DSP_DWNLD 2
#define PATCH_DSP_DWNLD 3
// MAC-S status reporting to Layer 1
#define MACS_STATUS 0 // MAC-S STATUS activated if set to 1
//---------------------------------------------------------------------------------
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -