📄 l1_confg.h
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/* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
/* 5 (830) | x | | | | 39Mhz | x | | | | 1 */
/* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
/* 6 (11xx) | x | x | x | x | 65Mhz | x | x (3)| |(2)| 3 */
/* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
/* */
/*(1) this version can be loaded on a 12LA68/POLE80 but the RIF/DL problem is*/
/* not corrected. */
/* */
/*(2) AEC is disabled at DSP level but L1 must be compiled with MCU/DSP */
/* interface which support AEC, therefore AEC is defined as 1. */
/* */
/*(3) Pole112 include RIF DL correction. No patch is needed if this one only */
/* include RIF/DL problem. */
/* */
/*---------------------------------------------------------------------------*/
#if (DSP == 16 || DSP == 17)
/* #define CLKMOD1 0x414e // ...
#define CLKMOD2 0x414e // ...65 Mips
#define CLKSTART 0x29 // ...65 Mips */
#define CLKMOD1 0x4006 // ...
#define CLKMOD2 0x4116 // ...65 Mips pll free
#define CLKSTART 0x29 // ...65 Mips
/* #define CLKMOD1 0x2116 //This settings force the DSP to never enteridle
#define CLKMOD2 0x2116 //In this case the PLL will be always on. 39 Mips
#define CLKSTART 0x25 // ...39 Mips */
#define VOC FR_HR_EFR // FR + HR + EFR.
#define DATA14_4 1 // No 14.4 data allowed.
#define AEC 1 // AEC/NS supported.
#define MAP 3
#define DSP_START 0x2000
#define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
#define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
/* DSP debug trace configuration */
/*-------------------------------*/
#if (MELODY_E2)
// In case of the melody E2 the DSP trace must be disable because the
// melody instrument waves are overlayed with DSP trace buffer
// DSP debug trace API buufer config
#define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
#define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
#else
// DSP debug trace API buufer config
#define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
#define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
#endif
#elif (DSP == 30) // First GPRS.
#define CLKMOD1 0x4006 // ...
#define CLKMOD2 0x4116 // ...65 Mips pll free
#define CLKSTART 0x29 // ...65 Mips
#define VOC FR_HR_EFR // FR + HR + EFR.
#define DATA14_4 1 // No 14.4 data allowed.
#define AEC 1 // AEC/NS not supported.
#define MAP 3
#define DSP_START 0x1F81
#define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
#define ULYSSE 0
#define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
#elif (DSP == 31) // ROM Code GPRS G0.
#define CLKMOD1 0x4006 // ...
#define CLKMOD2 0x4116 // ...65 Mips pll free
#define CLKSTART 0x29 // ...65 Mips
#define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
#define DATA14_4 1 // 14.4 data allowed.
#define AEC 1 // AEC/NS not supported.
#define MAP 3
#define DSP_START 0x8763
#define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
#define INSTALL_ADD_WITH_PATCH 0x1352 // Used to set gprs_install_address pointer
#define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
#define ULYSSE 0
#define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
#elif (DSP == 32) // ROM Code GPRS G1.
#define CLKMOD1 0x4006 // ...
#define CLKMOD2 0x4116 // ...65 Mips pll free
#define CLKSTART 0x29 // ...65 Mips
#define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
#define DATA14_4 1 // 14.4 data allowed.
#define AEC 1 // AEC/NS not supported.
#define MAP 3
#define DSP_START 0x8763
#define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
#define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
#define ULYSSE 0
#define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
#elif (DSP == 33) // ROM Code GPRS.
#define CLKMOD1 0x4006 // ...
#define CLKMOD2 0x4116 // ...65 Mips pll free
#define CLKSTART 0x29 // ...65 Mips
#define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
#define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
#define AEC 1 // AEC/NS not supported.
#if (OP_RIV_AUDIO == 0)
#define L1_NEW_AEC 1
#else
// Not yet available with Riviera AUDIO
#define L1_NEW_AEC 0
#endif
#if ((L1_NEW_AEC) && (!AEC))
// First undef the flag to avoid warnings at compilation time
#undef AEC
#define AEC 1
#endif
#define MAP 3
#define DSP_START 0x7000
#define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
#define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
#define ULYSSE 0
#define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
#if ((CHIPSET != 10) && (CHIPSET != 11) && (CHIPSET != 12))
#define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
// management.
#else
#define W_A_DSP_IDLE3 0
#endif
// DSP software work-around config
// bit0 - Work-around to support CRTG.
// bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
// bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
// bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
#if (ANALOG == 1) // OMEGA / NAUSICA
#define C_DSP_SW_WORK_AROUND 0x0006
#elif (ANALOG == 2) // IOTA
#define C_DSP_SW_WORK_AROUND 0x000E
#elif (ANALOG == 3) // SYREN
#define C_DSP_SW_WORK_AROUND 0x000E
#endif
/* DSP debug trace configuration */
/*-------------------------------*/
#if (MELODY_E2)
// In case of the melody E2 the DSP trace must be disable because the
// melody instrument waves are overlayed with DSP trace buffer
// DSP debug trace API buufer config
#define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
#define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
// DSP debug trace type config
// |<-------------- Features -------------->|<---------- Levels ----------->|
// [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
#define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
#if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
#define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
// Currently not supported !
#endif
#else
// DSP debug trace API buufer config
#define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
#define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
// DSP debug trace type config
// |<-------------- Features -------------->|<---------- Levels ----------->|
// [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
#define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
#if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
#define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
#endif
#endif
/* d_error_status */
/*-------------------------------*/
#if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
#define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
// masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
#define DSP_DEBUG_GSM_MASK 0x0000
#define DSP_DEBUG_GPRS_MASK 0x0f3d
#endif
#if DCO_ALGO
// DCO type of scheduling
#define C_CN_DCO_PARAM 0xA248
#endif
#elif (DSP == 34) // ROM Code GPRS AMR.
#define CLKMOD1 0x4006 // ...
#define CLKMOD2 0x4116 // ...65 Mips pll free
#define CLKSTART 0x29 // ...65 Mips
#define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
#define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
#define AEC 1 // AEC/NS not supported.
#if (OP_RIV_AUDIO == 0)
#define L1_NEW_AEC 1
#else
// Not yet available with Riviera AUDIO
#define L1_NEW_AEC 0
#endif
#if ((L1_NEW_AEC) && (!AEC))
// First undef the flag to avoid warnings at compilation time
#undef AEC
#define AEC 1
#endif
#define MAP 3
#define DSP_START 0x7000
#define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
#define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
#define ULYSSE 0
#define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
#if ((CHIPSET != 10) && (CHIPSET != 11) && (CHIPSET != 12))
#define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
// management.
#else
#define W_A_DSP_IDLE3 0
#endif
// DSP software work-around config
// bit0 - Work-around to support CRTG.
// bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
// bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
// bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
#if (ANALOG == 1) // OMEGA / NAUSICA
#define C_DSP_SW_WORK_AROUND 0x0006
#elif (ANALOG == 2) // IOTA
#define C_DSP_SW_WORK_AROUND 0x000E
#elif (ANALOG == 3) // SYREN
#define C_DSP_SW_WORK_AROUND 0x000E
#endif
/* DSP debug trace configuration */
/*-------------------------------*/
#if (MELODY_E2)
// In case of the melody E2 the DSP trace must be disable because the
// melody instrument waves are overlayed with DSP trace buffer
// DSP debug trace API buufer config
#define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
#define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
// DSP debug trace type config
// |<-------------- Features -------------->|<---------- Levels ----------->|
// [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
#define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
#if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
#define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
// Currently not supported !
#endif
#else
// DSP debug trace API buufer config
#define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
#define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
// DSP debug trace type config
// |<-------------- Features -------------->|<---------- Levels ----------->|
// [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
#define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
#if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
#define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
#endif
// AMR trace
#define C_AMR_TRACE_ID 55
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