l1_rf10.h

是一个手机功能的模拟程序

/************* Revision Controle System Header *************
 *                  GSM Layer 1 software
 *
 *        Filename l1_rf10.h
 *        Version  1.18
 *        Date     01/21/03
 * 
 ************* Revision Controle System Header *************/

 // is this defined somewhere else?
 //#define RF_HW_BAND_EGSM
 //#define RF_HW_BAND_DCS
 #define RF_HW_BAND_PCS 0x4
#define RF_HW_BAND_DUAL_US  0x80
#define RF_HW_BAND_DUAL_EXT 0x20

 #define RF_HW_BAND_SUPPORT (RF_HW_BAND_DUAL_EXT | RF_HW_BAND_PCS)  // radio_band_support E-GSM/DCS + PCS
/************************************/
/* SYNTHESIZER setup time...        */
/************************************/
#define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1)//RX Synthesizer setup time in qbit.
#define TX_SYNTH_SETUP_TIME (- TRF_T1)               //TX Synthesizer setup time in qbit.

/************************************/
/* time for TPU scenario ending...  */
/************************************/
#define RX_TPU_SCENARIO_ENDING  0                     // execution time of BDLENA down
                                                      // contained in serialization time
#define TX_TPU_SCENARIO_ENDING  DLT_1B - SL_SU_DELAY2 + 1 // execution time of BULON down
                                                          // minus serialization time + 1 TPU_MOVE

/******************************************************/
/* TXPWR configuration...                             */
/* Fixed TXPWR value when GSM management is disabled. */
/******************************************************/
#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
//  #define FIXED_TXPWR       0x3f12  // TXPWR=10, value=252
//#define FIXED_TXPWR       0x1952  
  #define FIXED_TXPWR       0x1d12  // TXPWR=15
#endif


/************************************/
/* ANALOG delay (in qbits)          */
/************************************/
#define  DL_DELAY_RF      1   // time spent in the Downlink global RF chain by the modulated signal 
#define  UL_DELAY_1RF     5   // time spent in the first  uplink RF block
#define  UL_DELAY_2RF     0   // time spent in the second uplink RF block
#if (ANALOG == 1)
  #define  UL_ABB_DELAY   6   // modulator input to output delay
#endif
#if ((ANALOG == 2) || (ANALOG == 3))
  #define  UL_ABB_DELAY   3   // modulator input to output delay
#endif

/************************************/
/* TX Propagation delay...          */
/************************************/
#if (ANALOG == 1)
  #define  PRG_TX       (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY)   // = 40
#endif
#if (ANALOG == 2) || (ANALOG == 3)
  #define  PRG_TX       (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY + 2)   // = 42
#endif

/************************************/
/* Initial value for APC DELAY      */
/************************************/
#if (ANALOG == 1)
//#define APCDEL_DOWN     (32 - GUARD_BITS*4)          // minimum value: 2
  #define APCDEL_DOWN      2                           // minimum value: 2
  #define APCDEL_UP       (6+5)                        // minimum value: 6
#endif
#if (ANALOG == 2) || (ANALOG == 3)
//#define APCDEL_DOWN     (32 - GUARD_BITS*4)          // minimum value: 2
  #define APCDEL_DOWN     (2+0)                        // minimum value: 2
  #define APCDEL_UP       (6+8)                        // minimum value: 6
#endif

#define GUARD_BITS 8

/************************************/
/* Initial value for AFC...         */
/************************************/
#define  EEPROM_AFC    ((150)*8)      // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced)

#define  SETUP_AFC_AND_RF   6  // AFC converges in 2 frames
                               // Clara (RF=10) LDO wakeup requires 3 frames

/************************************/
/* Baseband registers               */
/************************************/
#if (ANALOG == 1)
  // Omega registers values will be programmed at 1st DSP communication interrupt
  #define  C_DEBUG1          0x0000          // Enable f_tx delay of 400000 cyc DEBUG 
  #define  C_AFCCTLADD       0x002a | TRUE   // Value at reset
  #define  C_VBUR            0x418e | TRUE   // Uplink gain amp 0dB, Sidetone gain to mute
  #define  C_VBDR            0x098c | TRUE   // Downlink gain amp 0dB, Volume control 0 dB
  #define  C_APCOFF          0x1016 | (0x3c << 6) | TRUE   // value at reset-Changed from 0x0016- CR 27.12
  #define  C_BULIOFF         0x3fc4 | TRUE   // value at reset
  #define  C_BULQOFF         0x3fc6 | TRUE   // value at reset
  #define  C_DAI_ON_OFF      0x0000          // value at reset
  #define  C_AUXDAC          0x0018 | TRUE   // value at reset
  #define  C_VBCR            0x02d0 | TRUE   // VULSWITCH=1, VDLAUX=1, VDLEAR=1 
  // BULRUDEL will be initialized on rach only ....
  #define  C_APCDEL          (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004) 
  #define  C_BBCTL           0x604c | TRUE   // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
#endif
#if (ANALOG ==2)
  // IOTA registers values will be programmed at 1st DSP communication interrupt
  #define  C_DEBUG1          0x0001          // Enable f_tx delay of 400000 cyc DEBUG 
  #define  C_AFCCTLADD       0x002a | TRUE   // Value at reset
  #define  C_VBUR            0x418e | TRUE   // No uplink mute, Side tone mute, PGA_UL 0dB
  #define  C_VBDR            0x098c | TRUE   // PGA_DL 0dB, Volume 0dB
  #define  C_APCOFF          0x1016 | (0x28 << 6) | TRUE  // value at reset-Changed from 3c to 28 CR 17.11.02// x2 slope 128
  #define  C_BULIOFF         0x3fc4 | TRUE   // value at reset
  #define  C_BULQOFF         0x3fc6 | TRUE   // value at reset
  #define  C_DAI_ON_OFF      0x0000          // value at reset
  #define  C_AUXDAC          0x0018 | TRUE   // value at reset
  #define  C_VBCR            0x02d0 | TRUE   // VULSWITCH=1, VDLAUX=1, VDLEAR=1 
  #define  C_VBCR2           0x0016 | TRUE   // MICBIASEL=0, VDLHSO=0, MICAUX=0
  // BULRUDEL will be initialized on rach only ....
  #define  C_APCDEL          (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004)  
  #define  C_APCDEL2         0x0034  
  #define  C_BBCTL           0xb04c | TRUE   // External RX I/Q DC offset calibration, Output common mode=1.35V
                                             // Monoslot, Vpp=8/15*Vref                                             
  #define  C_BULGCAL         0x001c | TRUE   // IAG=0 dB, QAG=0 dB
#endif

#if (ANALOG == 3)
  // SYREN registers values will be programmed at 1st DSP communication interrupt
  #define  C_DEBUG1          0x0001          // Enable f_tx delay of 400000 cyc DEBUG 
  #define  C_AFCCTLADD       0x002a | TRUE   // Value at reset
  #define  C_VBUR            0x1E6<<6 | VBUCTRL | TRUE   //  Side tone mute, PGA_UL 0dB
  #define  C_VBDR            0x026<<6 | VBDCTRL | TRUE   // PGA_DL 0dB, Volume 0dB
  #define  C_APCOFF          0x1016 | (0x3c << 6) | TRUE   // x2 slope 128, APCSWP = 0
  #define  C_BULIOFF         0x3fc4 | TRUE   // value at reset
  #define  C_BULQOFF         0x3fc6 | TRUE   // value at reset
  #define  C_DAI_ON_OFF      0x0000          // value at reset
  #define  C_AUXDAC          (0x00<<6) | 0x18 | TRUE   // value at reset
  #define  C_VBCR            (0x108<<6) | 0x10 | TRUE   // VULSWITCH=1 AUXI 28,2 dB
  #define  C_VBCR2           (0x01<<6) | 0x16 | TRUE   // HSMIC on, SPKG gain @ 2,5dB
  // BULRUDEL will be initialized on rach only ....
  #define  C_APCDEL          (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004)  
  #define  C_APCDEL2         0x0034  
  #define  C_BBCTL           0xB04c | TRUE   // External autocalibration, Output common mode=1.35V
                                             // Monoslot, Vpp=8/15*Vref                                             
  #define  C_BULGCAL         0x001c | TRUE   // IAG=0 dB, QAG=0 dB

  #define  C_VBPOP           (0x4)<<6 | 0x14 | TRUE     // HSOAUTO enabled only
  #define  C_VAUDINITD       2                          // vaud_init_delay init 2 frames
  #define  C_VAUDCR          (0x0)<<6   | 0x1e | TRUE   // Init to zero
  #define  C_VAUOCR          (0x155)<<6 | VAUOCTRL | TRUE   // Sppech on all outputs
  #define  C_VAUSCR          (0x0)<<6   | 0x20 | TRUE   // Init to zero
  #define  C_VAUDPLL         (0x0)<<6   | 0x24 | TRUE   // Init to zero

#endif


/************************************/
/* Automatic frequency compensation */
/************************************/
/********************* C_Psi_sta definition *****************************/
/* C_Psi_sta = (2*pi*Fr)        / (N * Fb)                              */
/*      (1)  = (2*pi*V*ppm*0.9) / (N*V*Fb)                              */
/*           regarding Vega V/N   = 2.4/4096                            */
/*           regarding VCO  ppm/V = 16 / 1   (average slope of the VCO) */
/*      (1)  = (2*pi*2.4*16*0.9) / (4096*1*270.83)                      */
/*           = 0.000195748                                              */
/* C_Psi_sta_inv = 1/C_Psi_sta = 5108                                   */
/************************************************************************/
#define  C_Psi_sta_inv    4174L    // (1/C_Psi_sta)                   
#define  C_Psi_st         13L        // C_Psi_sta * 0.8 F0.16          
#define  C_Psi_st_32      823216L  // F0.32                          
#define  C_Psi_st_inv     5217L   // (1/C_Psi_st)                   

#if (VCXO_ALGO == 1)
  // Linearity parameters
  #define  C_AFC_DAC_CENTER     ((111)*8)
  #define  C_AFC_DAC_MIN        ((-1196)*8)
  #define  C_AFC_DAC_MAX        ((1419)*8)

  #define  C_AFC_SNR_THR        2560     //  1/0.4    * 2**10
#endif

typedef struct
{
  WORD16  eeprom_afc;
  UWORD32 psi_sta_inv;
  UWORD32 psi_st;
  UWORD32 psi_st_32;
  UWORD32 psi_st_inv;

  #if (VCXO_ALGO == 1)
    // VCXO adjustment parameters
    // Parameters used when assuming linearity
    WORD16  dac_center;
    WORD16  dac_min;
    WORD16  dac_max;
    WORD16  snr_thr;
  #endif
}
T_AFC_PARAMS;

/************************************/
/* Swap IQ definitions...           */
/************************************/
/* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
#define  SWAP_IQ_GSM  0
#define  SWAP_IQ_DCS  2  // was 2 for sara version 1
#define  SWAP_IQ_PCS    2   
#define  SWAP_IQ_GSM850 0   //TBD

/************************************/
/************************************/
// typedef
/************************************/
/************************************/

/*************************************************************/
/* Define structure for apc of TX Power                 ******/
/*************************************************************/
typedef struct 
{ // pcm-file "rf/tx/level.gsm|dcs"
  UWORD16 apc;            // 0..31
  UWORD8  ramp_index;     // 0..RF_TX_RAMP_SIZE
  UWORD8  chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
} 
T_TX_LEVEL;

/************************************/
/* Automatic Gain Control           */
/************************************/
/* Define structure for sub-band definition of TX Power ******/ 
typedef struct 
   {
   UWORD16  upper_bound;    //highest physical arfcn of the sub-band 
   WORD16    agc_calib;      // AGC  for each TXPWR
   }T_RF_AGC_BAND;

/************************************/
/*       Ramp definitions           */
/************************************/
#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
  typedef struct
  {
    UWORD8  ramp_up     [16];  // Ramp-up profile
    UWORD8  ramp_down   [16];  // Ramp-down profile
  }
  T_TX_RAMP;
#endif


// RF structure definition
//========================

enum RfRevision {
    RF_IGNORE      = 0x0000,
    RF_SL2         = 0x1000,
    RF_GAIA_20X    = 0x2000,
    RF_GAIA_20A    = 0x2001,
    RF_GAIA_20B    = 0x2002,
    RF_ATLAS_20B   = 0x2020,
    RF_PASCAL_20   = 0x2030
};

// Number of bands supported
#define GSM_BANDS 2

#define MULTI_BAND1     0
#define MULTI_BAND2     1
// RF table sizes
#define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands
#define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges

#define RF_TX_CHAN_CAL_TABLE_SIZE  4 // channel calibration table size 
#define RF_TX_NUM_SUB_BANDS        8 // number of sub-bands in channel calibration table
#define RF_TX_LEVELS_TABLE_SIZE   32 // level table size  
#define RF_TX_RAMP_SIZE           16 // number of ramp definitions
#define RF_TX_CAL_TEMP_SIZE        5 // number of temperature ranges