madevdrv.c

是一个手机功能的模拟程序

}
/****************************************************************************
 *	MaDevDrv_SendDelayedPacket
 *
 *	Description:
 *			Write delayed packets to the REG_ID #1 delayed write register.
 *	Argument:
 *			pbData	pointer to the delayed packets
 *			dSize	size of the delayed packets
 *	Return:
 *			0		success
 *			< 0		error code
 *
 ****************************************************************************/
SINT32 MaDevDrv_SendDelayedPacket( const UINT8 * pbData, UINT32 dSize )
{
	MADEVDRV_DBGMSG(("    MaDevDrv_SendDelayedPacket: pt=%p, sz=%d\n", pbData, dSize));

	if( dSize == 0 )  return MASMW_SUCCESS;

	/* increment Irq access counter */
	pgMaDevDrvInfo->bMaskInterrupt++;

	/* set REG_ID #1   */
	WriteStatusFlagReg( MAI_DELAYED_WRITE );

	/* write data */
	machdep_WriteDataRegN( (UINT8*)pbData, dSize );

	/* enable interrupt if needed */
	if ( (--pgMaDevDrvInfo->bMaskInterrupt)==0 )
	{
		WriteStatusFlagReg( MAB_IRQ_ENABLE );
	}

	return MASMW_SUCCESS;
}
/****************************************************************************
 *	MaDevDrv_SendDirectRamData
 *
 *	Description:
 *			write data to internal RAM.
 *	Arguments:
 *			dAddress  internal RAM address
 *			dType	  type of data 0:8bit data , 1:7bit encoded data
 *			pbData	  pointer ot the write byte data to internal RAM
 *			dSize	  size of write byte data to internal RAM
 *	Return:
 *			0		  success
 *			< 0		  error code
 *
 ****************************************************************************/
SINT32 MaDevDrv_SendDirectRamData( UINT32 dAddress, UINT8 bType, 
											const UINT8 *pbData, UINT32 dSize)
{
	UINT32	i, j;
	UINT32	dWriteSize;
	UINT8	bWriteData;
	UINT8	bTemp = 0;
	SINT32	sdResult;

	MADEVDRV_DBGMSG(("    MaDevDrv_SendDirectRamData: adrs=%04lX type=%d ptr=%p size=%ld\n", dAddress, bType, pbData, dSize));

	if ( dSize == 0 ) return MASMW_SUCCESS;

	/* size */
	if ( bType == 0 )			/* 8bit data */
	{
		dWriteSize = dSize;
	}
	else						/* 7bit encoded data */
	{
		dWriteSize = (dSize / 8) * 7;
		if ( dSize % 8 != 0 )
			dWriteSize = (UINT32)( dWriteSize + (dSize % 8 - 1) );
	}

	if( dAddress+dWriteSize>MA_MEMORY_SIZE ) return MASMW_ERROR;

	/* increment Irq access counter */
	pgMaDevDrvInfo->bMaskInterrupt++;

	/* set REG_ID #2   */
	WriteStatusFlagReg( MAI_IMMEDIATE_WRITE );

	/* check status */
	sdResult = machdep_WaitImmediateFifoEmpty();

	/* error */
	if ( sdResult < MASMW_SUCCESS )
	{
		/* enable interrupt if needed */
		MaDevDrv_EnableIrq();
		return sdResult;
	}

	/* write direct packet */

	/* Address part */
	machdep_WriteDataReg( (UINT8)((dAddress >>  0 ) & 0x7F) );
	machdep_WriteDataReg( (UINT8)((dAddress >>  7 ) & 0x7F) );
	machdep_WriteDataReg( (UINT8)((dAddress >> 14 ) | 0x80) );

	/* size */
	if	( dWriteSize < 0x0080 )
	{
		machdep_WriteDataReg( (UINT8)( (dWriteSize >> 0) | 0x80 ) );
	}
	else
	{
		machdep_WriteDataReg( (UINT8)( (dWriteSize >> 0) & 0x7F ) );
		machdep_WriteDataReg( (UINT8)( (dWriteSize >> 7) | 0x80 ) );
	}

	/* Type 0, 8bit data */
	if ( bType == 0 )
	{
		i = dSize/64;
		while ( (i--) != 0 )
		{
			/* check status */
			sdResult = machdep_WaitImmediateFifoEmpty();

			/* error  */
			if ( sdResult < MASMW_SUCCESS )
			{
				/* enable interrupt if needed */
				MaDevDrv_EnableIrq();
				return sdResult;
			}

			/* write 64 bytes data */
			machdep_WriteDataRegN( (UINT8*)pbData, (UINT32)64 );
			pbData += 64;
		}

		/* write odd data */
		if ( (j=(dSize%64)) != 0 )
		{
			/* check status */
			sdResult = machdep_WaitImmediateFifoEmpty();

			/* error  */
			if ( sdResult < MASMW_SUCCESS )
			{
				/* enable interrupt if needed */
				MaDevDrv_EnableIrq();
				return sdResult;
			}
			/* write data */
			machdep_WriteDataRegN( (UINT8*)pbData, j );
		}
	}
	/* Type 1, 7bit encoded data */
	else
	{
		for ( i = 0; i < dSize; i++ )
		{
			if ( (i & 0xFFFFFFC0) == 0 )
			{
				/* check status */
				sdResult = machdep_WaitImmediateFifoEmpty();

				/* error  */
				if ( sdResult < MASMW_SUCCESS )
				{
					/* enable interrupt if needed */
					MaDevDrv_EnableIrq();
					return sdResult;
				}
			}

			if ( ( i % 8 ) == 0 )
			{
				bTemp = *pbData++;
			}
			else
			{
				bWriteData = *pbData++;
				bWriteData |= (UINT8)( ( bTemp << (i % 8) ) & 0x80 );

				/* write data */
				machdep_WriteDataReg( bWriteData );
			}
		}
	}

	/* enable interrupt if needed */
	if ( (--pgMaDevDrvInfo->bMaskInterrupt)==0 )
	{
		WriteStatusFlagReg( MAB_IRQ_ENABLE );
	}

	return MASMW_SUCCESS;
}
/****************************************************************************
 *	MaDevDrv_SendDirectRamVal
 *
 *	Description:
 *			Write specified data to internal RAM
 *	Arguments:
 *			dAddress  internal RAM address
 *			dSize	  size of write byte data to internal RAM
 *			bVal	  write byte data
 *	Return:
 *			0		  success
 *			< 0		  error code
 *
 ****************************************************************************/
SINT32 MaDevDrv_SendDirectRamVal( UINT32 dAddress, UINT32 dSize, UINT8 bVal )
{
	UINT32	i, j;						/* loop counter */
	SINT32	sdResult;					/* result of function */

	MADEVDRV_DBGMSG(("    MaDevDrv_SendDirectRamVal: adrs=%04lX size=%ld val=%02X\n", dAddress, dSize, bVal));

	if ( dSize == 0 ) return MASMW_SUCCESS;
	if ( dAddress+dSize>MA_MEMORY_SIZE ) return MASMW_ERROR;

	/* increment Irq access counter */
	pgMaDevDrvInfo->bMaskInterrupt++;

	/* set REG_ID #2   */
	WriteStatusFlagReg( MAI_IMMEDIATE_WRITE );

	/* check status */
	sdResult = machdep_WaitImmediateFifoEmpty();

	/* error  */
	if ( sdResult < MASMW_SUCCESS )
	{
		/* enable interrupt if needed */
		MaDevDrv_EnableIrq();
		return sdResult;
	}

	/* write direct packet */

	/* Address */
	machdep_WriteDataReg( (UINT8)((dAddress >>  0 ) & 0x7F) );
	machdep_WriteDataReg( (UINT8)((dAddress >>  7 ) & 0x7F) );
	machdep_WriteDataReg( (UINT8)((dAddress >> 14 ) | 0x80) );

	/* Size */
	if ( dSize < 0x0080 )
	{
		machdep_WriteDataReg( (UINT8)( (dSize >> 0) | 0x80 ) );
	}
	else
	{
		machdep_WriteDataReg( (UINT8)( (dSize >> 0) & 0x7F ) );
		machdep_WriteDataReg( (UINT8)( (dSize >> 7) | 0x80 ) );
	}

	i = dSize/64;

	while ( (i--) != 0 )
	{
		/* check status */
		sdResult = machdep_WaitImmediateFifoEmpty();

		/* error  */
		if ( sdResult < MASMW_SUCCESS )
		{
			/* enable interrupt if needed */
			MaDevDrv_EnableIrq();
			return sdResult;
		}

		/* write 64 bytes data */
		machdep_WriteDataRegValN( bVal, (UINT32)64 );
	}

	/* write remained data(<64) */
	if ( (j=(dSize%64)) != 0 )
	{
		/*check status */
		sdResult = machdep_WaitImmediateFifoEmpty();

		/* error  */
		if ( sdResult < MASMW_SUCCESS )
		{
			/* enable interrupt if needed */
			MaDevDrv_EnableIrq();
			return sdResult;
		}

		/* write data */
		machdep_WriteDataRegValN( bVal, j );
	}

	/* enable interrupt if needed */
	if ( (--pgMaDevDrvInfo->bMaskInterrupt)==0 )
	{
		WriteStatusFlagReg( MAB_IRQ_ENABLE );
	}

	return MASMW_SUCCESS;
}
/****************************************************************************
 *	MaDevDrv_StartSequencer
 *
 *	Description:
 *			Start sequencer.
 *	Argument:
 *			sdSeqId	 sequence id
 *	Return:
 *			0		 success
 *			< 0		 error code
 *
 ****************************************************************************/
SINT32 MaDevDrv_StartSequencer( SINT32 sdSeqId )
{
	SINT32	sdResult;						/* sdResult of function */

	MADEVDRV_DBGMSG(("MaDevDrv_StartSequencer: seq_id=%ld\n", sdSeqId));

	sdResult = MASMW_SUCCESS;

	/* increment Irq access counter */
	pgMaDevDrvInfo->bMaskInterrupt++;

	/* set REG_ID #0   */
	WriteStatusFlagReg( MAI_IRQ_FLAG_1 );

	switch ( sdSeqId )
	{
	case 0:						/* delayed sequence */
		/* Pending FIFO IRQ */
		if( pgMaDevDrvInfo->dPendingIrq & 0x80 ) {
			pgMaDevDrvInfo->pIntFunc[7](0);
			pgMaDevDrvInfo->dPendingIrq &= ~0x80;
		}
		/* Pending SINRQ#2 IRQ */
		if( pgMaDevDrvInfo->dPendingIrq & 0x400 ) {
			pgMaDevDrvInfo->pIntFunc[8](0);
			pgMaDevDrvInfo->dPendingIrq &= ~0x400;
		}
		/* Pending SINRQ#3 IRQ */
		if( pgMaDevDrvInfo->dPendingIrq & 0x800 ) {
			pgMaDevDrvInfo->pIntFunc[9](0);
			pgMaDevDrvInfo->dPendingIrq &= ~0x800;
		}
		/* Enable FIFO IRQ */
		ControlInterrupt( MAI_IRQ_CONTROL_1, ENABLE_IRQ, MAB_IRQCTRL_EFIFO );

		/* Start H/W Sequencer */
		pgMaDevDrvInfo->dActiveSequencer |= MADEVDRV_ACTIVE_DELAYEDSEQ;
		MaDevDrv_WriteIntermediateReg( MAI_SEQ_CTRL, 0x01 );
		break;

	case 1:						/* Phrase */
		/* Start Timer#2A */
		pgMaDevDrvInfo->dActiveSequencer |= MADEVDRV_ACTIVE_PHRASESEQ;
		MaDevDrv_WriteIntermediateReg( MAI_TIMER2_TMSTA, 0x01 );
		break;

	case 2:						/* HV */
		/* Start Timer#2B */
		pgMaDevDrvInfo->dActiveSequencer |= MADEVDRV_ACTIVE_HVSEQ;
		MaDevDrv_WriteIntermediateReg( MAI_TIMER2_TMSTB, 0x01 );
		break;

	default:
		sdResult = MASMW_ERROR_ARGUMENT;
		break;
	}

	/* enable interrupt if needed */
	if ( (--pgMaDevDrvInfo->bMaskInterrupt)==0 )
	{
		WriteStatusFlagReg( MAB_IRQ_ENABLE );
	}

	return sdResult;
}
/****************************************************************************
 *	MaDevDrv_StopSequencer
 *
 *	Description:
 *			Stop sequencer.
 *	Argument:
 *			sdSeqId	 sequence id
 *	Return:
 *			0		 success
 *			< 0		 error code
 *
 ****************************************************************************/
SINT32 MaDevDrv_StopSequencer( SINT32 sdSeqId )
{
	SINT32	sdResult;

	MADEVDRV_DBGMSG(("MaDevDrv_StopSequencer: seq_id=%ld\n", sdSeqId));

	sdResult = MASMW_SUCCESS;

	/* increment Irq access counter */
	pgMaDevDrvInfo->bMaskInterrupt++;

	/* set REG_ID #0   */
	WriteStatusFlagReg( MAI_IRQ_FLAG_1 );

	switch ( sdSeqId )
	{
	case 0:						/* delayed sequence */
		/* Disable FIFO/StreamPG IRQ */
		ControlInterrupt( MAI_IRQ_CONTROL_1, DISABLE_IRQ, MAB_IRQCTRL_EFIFO |
										 MAB_IRQCTRL_ESTM1|MAB_IRQCTRL_ESTM0 );

		pgMaDevDrvInfo->dActiveSequencer &= ~MADEVDRV_ACTIVE_DELAYEDSEQ;
		/* Stop Sequencer */
		MaDevDrv_WriteIntermediateReg( MAI_SEQ_CTRL, 0x00 );
		
#ifdef COLORLED_SUPPORT
		/* output to CPU GPIO */
		Red_Off();
		Blue_Off();
		Green2_Off();
#endif		
	
		break;

	case 1:						/* Phrase */
		pgMaDevDrvInfo->dActiveSequencer &= ~MADEVDRV_ACTIVE_PHRASESEQ;
		/* Stop Timer#2A */
		MaDevDrv_WriteIntermediateReg( MAI_TIMER2_TMSTA, 0x00 );
		break;

	case 2:						/* HV	*/
		pgMaDevDrvInfo->dActiveSequencer &= ~MADEVDRV_ACTIVE_HVSEQ;
		/*Stop Timer#2B */
		MaDevDrv_WriteIntermediateReg( MAI_TIMER2_TMSTB, 0x00 );
		break;

	default:
		sdResult = MASMW_ERROR_ARGUMENT;
		break;
	}

	/* enable interrupt if needed */
	if ( (--pgMaDevDrvInfo->bMaskInterrupt)==0 )
	{
		WriteStatusFlagReg( MAB_IRQ_ENABLE );
	}

	return sdResult;
}
/****************************************************************************
 *	MaDevDrv_EndofSequence
 *
 *	Description:
 *			End of Sequence.
 *	Argument:
 *			None
 *	Return:
 *			0		success
 *			< 0		error code
 *
 ****************************************************************************/
SINT32 MaDevDrv_EndofSequence( void )
{
	MADEVDRV_DBGMSG(("MaDevDrv_EndofSequence\n"));

	pgMaDevDrvInfo->dEndofSequence = 1;
	return MASMW_SUCCESS;
}
/****************************************************************************
 *	MaDevDrv_ClearFifo
 *
 *	Description:
 *			Clear Delayed FIFO.
 *	Argument:
 *			None
 *	Return:
 *			0		success
 *			< 0		error code
 *
 ****************************************************************************/
SINT32 MaDevDrv_ClearFifo( void )
{
	SINT32	i;

	MADEVDRV_DBGMSG(("MaDevDrv_ClearFifo\n"));

	/* increment Irq access counter */
	pgMaDevDrvInfo->bMaskInterrupt++;

	/* set REG_ID #4   */
	WriteStatusFlagReg( MAI_BASIC_SETTING );

	/* set RFIF0 and RSEQ0 bit */
	machdep_WriteDataReg( MAB_RFIFO0|MAB_RSEQ0 );
	/* wait 300ns */
	machdep_Wait( 300 );
	/* reset RFIF0 and RSEQ0 bit */
	machdep_WriteDataReg( 0x00 );

	/* clear Read/Write buffer pointer */
	pgMaDevDrvInfo->SbufInfo.dWriteNum = 0;
	pgMaDevDrvInfo->SbufInfo.dReadNum  = 0;

	/* clear software buffer size */
	for ( i = 0; i < MA_SBUF_NUM; i++ )
	{