📄 madevdrv.c
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return MASMW_SUCCESS;
}
/****************************************************************************
* MaDevDrv_PowerManagement
*
* Description:
* Power management.
* Argument:
* mode 0: Hardware initialize sequence (power down)
* 1: Hardware initialize sequence (normal)
* 2: Power down change sequence
* 3: Power down release sequence
* Return:
* 0 success
* < 0 error code
*
****************************************************************************/
SINT32 MaDevDrv_PowerManagement
(
UINT8 mode /* operation mode */
)
{
UINT8 count; /* loop counter */
SINT32 result = MASMW_SUCCESS; /* result of function */
MADEVDRV_DBGMSG(("MaDevDrv_PowerManagement: mode=%d\n", mode));
switch ( mode )
{
case 0:
/* sequence of hardware initialize when power downed */
/* set BANK bits of REG_ID #4 basic setting register to '0' */
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG );
machdep_WriteDataReg( 0x00 );
/* set DP0 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 | MA_DP2 | MA_DP1 );
/* set PLLPD bit of power management (A) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_ANALOG_REG );
machdep_WriteDataReg( MA_AP4R | MA_AP4L | MA_AP3 | MA_AP2 | MA_AP1 | MA_AP0 );
/* wait 10ms */
machdep_Wait( 10 * 1000 * 1000 );
/* set DP1 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 | MA_DP2 );
/* set DP2 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteDataReg( MA_DP3 );
for ( count = 0; count < MA_RESET_RETRYCOUNT; count++ )
{
/* set RST bit of REG_ID #4 basic setting register to '1' */
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG );
machdep_WriteDataReg( 0x80 );
/* set RST bit of REG_ID #4 basic setting register to '0' */
machdep_WriteDataReg( 0x00 );
/* wait 41.7us */
machdep_Wait( 41700 );
/* verify the initialized registers by software reset */
result = MaDevDrv_VerifyRegisters();
if ( result == MASMW_SUCCESS ) break;
}
/* set DP2 bit of REG_ID #5 power management (D) setting register to '1' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 | MA_DP2 );
/* set DP1 bit of REG_ID #5 power management (D) setting register to '1' */
machdep_WriteDataReg( MA_DP3 | MA_DP2 | MA_DP1 );
/* set PLLPD bit of REG_ID #6 power management (A) setting register to '1' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_ANALOG_REG );
machdep_WriteDataReg( MA_PLLPD | MA_AP4R | MA_AP4L | MA_AP3 | MA_AP2 | MA_AP1 | MA_AP0 );
/* set DP0 bit of REG_ID #5 power management (D) setting register to '1' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 | MA_DP2 | MA_DP1 | MA_DP0 );
/* enable interrupt if needed */
machdep_WriteStatusFlagReg( cinfo_ptr->mask_interrupt );
break;
case 1:
/* sequence of hardware initialize when normal */
/* set BANK bits of REG_ID #4 basic setting register to '0' */
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG );
machdep_WriteDataReg( 0x00 );
/* set DP0 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 | MA_DP2 | MA_DP1 );
/* set PLLPD and AP0 bits of REG_ID #6 power management (A) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_ANALOG_REG );
machdep_WriteDataReg( MA_AP4R | MA_AP4L | MA_AP3 | MA_AP2 | MA_AP1 );
machdep_Wait( 10 * 1000 * 1000 );
/* set DP1 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 | MA_DP2 );
/* set DP2 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteDataReg( MA_DP3 );
for ( count = 0; count < 10; count++ )
{
/* set RST bit of REG_ID #4 basic setting register to '1' */
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG );
machdep_WriteDataReg( 0x80 );
/* set RST bit of REG_ID #4 basic setting register to '0' */
machdep_WriteDataReg( 0x00 );
/* wait 41.7us */
machdep_Wait( 41700 );
/* Robert.Chen */
/* set DP3 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( 0x00 );
/* end */
/* verify the initialized registers by software reset */
result = MaDevDrv_VerifyRegisters();
if ( result == MASMW_SUCCESS ) break;
}
#if 0
/* set DP3 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( 0x00 );
#endif
/* set AP1, AP3 and AP4 bits of REG_ID #6 power management (A) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_ANALOG_REG );
machdep_WriteDataReg( MA_AP2 );
/* wait 10us */
machdep_Wait( 10 * 1000 );
/* set AP2 bit of REG_ID #6 power management (A) setting register to '0' */
machdep_WriteDataReg( 0x00 );
/* Robert.Chen */
machdep_WriteStatusFlagReg(0x5);
MADEVDRV_DBGMSG(("MelDrv:BANK0, Reg5 = 0x%02x", machdep_ReadDataReg()));
machdep_WriteStatusFlagReg(0x6);
MADEVDRV_DBGMSG(("MelDrv:BANK0, Reg6 = 0x%02x", machdep_ReadDataReg()));
/* end */
/* enable interrupt */
machdep_WriteStatusFlagReg( cinfo_ptr->mask_interrupt );
/* normal */
break;
case 2:
/* sequence of power down */
/* set BANK bits of REG_ID #4 basic setting register to '0' */
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG );
machdep_WriteDataReg( 0x00 );
/* set DP3 bit of REG_ID #5 power management (D) setting register to '1' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 );
/* set DP2 bit of REG_ID #5 power management (D) setting register to '1' */
machdep_WriteDataReg( MA_DP3 | MA_DP2 );
/* set DP1 bit of REG_ID #5 power management (D) setting register to '1' */
machdep_WriteDataReg( MA_DP3 | MA_DP2 | MA_DP1 );
/* set AP1, AP2, AP3, AP4 and PLLPD bits of REG_ID #6 power management (A) setting register to '1' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_ANALOG_REG );
machdep_WriteDataReg( MA_PLLPD | MA_AP4R | MA_AP4L | MA_AP3 | MA_AP2 | MA_AP1 | MA_AP0 );
/* set DP0 bit of REG_ID #5 power management (D) setting register to '1' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 | MA_DP2 | MA_DP1 | MA_DP0 );
/* enable interrupt */
machdep_WriteStatusFlagReg( cinfo_ptr->mask_interrupt );
break;
case 3:
/* set BANK bits of REG_ID #4 basic setting register to '0' */
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG );
machdep_WriteDataReg( 0x00 );
/* set DP0 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 | MA_DP2 | MA_DP1 );
/* set AP0 and PLLPD bits of REG_ID #6 power management (A) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_ANALOG_REG );
machdep_WriteDataReg( MA_AP4R | MA_AP4L | MA_AP3 | MA_AP2 | MA_AP1 );
/* wait 10ms */
machdep_Wait( 10 * 1000 * 1000 );
/* set DP1 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( MA_DP3 | MA_DP2 );
/* set DP2 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteDataReg( MA_DP3 );
/* set DP3 bit of REG_ID #5 power management (D) setting register to '0' */
machdep_WriteDataReg( 0x00 );
/* set AP1, AP3 and AP4 bits of REG_ID #6 power management (A) setting register to '0' */
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_ANALOG_REG );
machdep_WriteDataReg( MA_AP2 );
/* wait 10us */
machdep_Wait( 10 * 1000 );
/* set AP2 bit of REG_ID #6 power management (A) setting register to '0' */
machdep_WriteDataReg( 0x00 );
/* enable interrupt */
machdep_WriteStatusFlagReg( cinfo_ptr->mask_interrupt );
break;
default:
break;
}
return result;
}
/****************************************************************************
* MaDevDrv_DeviceControl
*
* Description:
* Control the device.
* Arguments:
* cmd command number (0..10)
* param1 1st parameter
* param2 2nd parameter
* param3 3rd parameter
* Return:
* None
*
* message cmd param1 param2 param3
* -------------------------------------------------------
* DIGITAL PWR 0 val
* ANALOG PWR 1 val
* EQVOL 2 val
* HPVOL 3 mono vol_l vol_r
* SPVOL 4 vol
* LED 5 led freq mode
* MOTOR 6 mtr freq mode
* PLL 7 adjust1 adjust2
* VOL MODE 8 mute chvol panpot
* EFFECT 9 prb
* FM MODE 10 mode
* GET SEQ STATUS 11
*
****************************************************************************/
SINT32 MaDevDrv_DeviceControl
(
UINT8 cmd, /* command number */
UINT8 param1, /* parameter 1 */
UINT8 param2, /* parameter 2 */
UINT8 param3 /* parameter 3 */
)
{
SINT32 seq_flag;
UINT8 packet[3];
MADEVDRV_DBGMSG((" MaDevDrv_DeviceControl: cmd=%d p1=%d p2=%d p3=%d\n", cmd, param1, param2, param3));
if ( cmd <= 6 )
{
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG );
machdep_WriteDataReg( 0x00 );
switch ( cmd )
{
case 0:
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_DIGITAL_REG );
machdep_WriteDataReg( param1 );
break;
case 1:
machdep_WriteStatusFlagReg( MA_POWER_MANAGEMENT_ANALOG_REG );
machdep_WriteDataReg( (UINT8)(param1 & 0xBF) );
break;
case 2:
machdep_WriteStatusFlagReg( MA_ANALOG_EQVOL_REG );
machdep_WriteDataReg( (UINT8)(param1 & 0x1F) );
break;
case 3:
machdep_WriteStatusFlagReg( MA_ANALOG_HPVOL_L_REG );
machdep_WriteDataReg( (UINT8)((param1<<7) | (param2&0x1F)) );
machdep_WriteStatusFlagReg( MA_ANALOG_HPVOL_R_REG );
machdep_WriteDataReg( param3 );
break;
case 4:
machdep_WriteStatusFlagReg( MA_ANALOG_SPVOL_REG );
machdep_WriteDataReg( (UINT8)((MA_VSEL<<6) | (param1&0x1F)) );
break;
case 5:
machdep_WriteStatusFlagReg( MA_LED_SETTING_1_REG );
machdep_WriteDataReg( (UINT8)(param1 & 0x3F) );
machdep_WriteStatusFlagReg( MA_LED_SETTING_2_REG );
machdep_WriteDataReg( (UINT8)((param2<<4) | (param3 & 0x07)) );
break;
case 6:
machdep_WriteStatusFlagReg( MA_MOTOR_SETTING_1_REG );
machdep_WriteDataReg( (UINT8)(param1 & 0x3F) );
machdep_WriteStatusFlagReg( MA_MOTOR_SETTING_2_REG );
machdep_WriteDataReg( (UINT8)((param2<<4) | (param3 & 0x07)) );
break;
}
machdep_WriteStatusFlagReg( cinfo_ptr->mask_interrupt );
}
else if ( cmd <= 7 )
{
machdep_WriteStatusFlagReg( MA_BASIC_SETTING_REG );
machdep_WriteDataReg( 0x01 );
machdep_WriteStatusFlagReg( MA_PLL_SETTING_1_REG );
machdep_WriteDataReg( (UINT8)(param1 & 0x1F) );
machdep_WriteStatusFlagReg( MA_PLL_SETTING_2_REG );
machdep_WriteDataReg( (UINT8)(param2 & 0x7F) );
machdep_WriteStatusFlagReg( cinfo_ptr->mask_interrupt );
}
else if ( cmd <= 10 )
{
switch ( cmd )
{
case 8: /* #355 smooth vol */
packet[0] = 0x63;
packet[1] = 0x82;
packet[2] = (UINT8)( 0x80 | (param1<<4) | (param2<<2) | param3 );
break;
case 9: /* #357 effects */
packet[0] = 0x65;
packet[1] = 0x82;
packet[2] = (UINT8)( 0x80 | param1 );
break;
case 10: /* #359 FM mode */
packet[0] = 0x67;
packet[1] = 0x82;
packet[2] = (UINT8)( 0x80 | param1 );
break;
}
MaDevDrv_SendDirectPacket( packet, 3 );
}
else if ( cmd == 11 )
{
machdep_WriteStatusFlagReg( 0x00 );
seq_flag = (SINT32)cinfo_ptr->stop_reg;
cinfo_ptr->stop_reg = 0;
machdep_WriteStatusFlagReg( cinfo_ptr->mask_interrupt );
return seq_flag;
}
else
{
return MASMW_ERROR;
}
return MASMW_SUCCESS;
}
/****************************************************************************
* MaDevDrv_Initialize
*
* Description:
* Initialize the MA Device Driver module.
* Arguments:
* None
* Return:
* 0 success
* -1 error
*
****************************************************************************/
SINT32 MaDevDrv_Initialize( void )
{
UINT32 i; /* loop counter */
SINT32 result; /* result of function */
MADEVDRV_DBGMSG(("MaDevDrv_Initialize\n"));
cinfo_ptr->seq_flag = 0;
cinfo_ptr->stop_reg = 0;
cinfo_ptr->stop_flag = 0;
cinfo_ptr->ctrl_seq = 0;
cinfo_ptr->timer0 = 0;
cinfo_ptr->mask_interrupt = 0x80;
cinfo_ptr->int_func_map = 0x00;
cinfo_ptr->audio_mode = 0;
for ( i = 0; i < 3; i++ )
{
cinfo_ptr->end_of_sequence[i] = 0; /* !! */
}
cinfo_ptr->sbuf_info.write_num = 0;
cinfo_ptr->sbuf_info.read_num = 0;
cinfo_ptr->sbuf_info.buf_total = 0;
cinfo_ptr->sbuf_info.buf_ptr = 0;
for ( i = 0; i < MA_SBUF_NUM; i++ )
{
cinfo_ptr->sbuf_info.buf_size[i] = 0;
}
for ( i = 0; i < MA_MAX_STREAM_AUDIO; i++ )
{
cinfo_ptr->streaminfo.state[i] = 0;
cinfo_ptr->streaminfo.write_block[i] = 0;
cinfo_ptr->streaminfo.read_block[i] = 0;
cinfo_ptr->streaminfo.format[i] = 0;
cinfo_ptr->streaminfo.wave_ptr[i] = NULL;
cinfo_ptr->streaminfo.wave_size[i] = 0;
cinfo_ptr->streaminfo.position[i] = 0;
cinfo_ptr->streaminfo.end_point[i] = 0;
cinfo_ptr->streaminfo.prv_point[i] = 0;
}
MaDevDrv_AddIntFunc( 0, MaDevDrv_SoftInt0 ); /* Soft Int #0 */
MaDevDrv_AddIntFunc( 1, MaDevDrv_SoftInt1 ); /* Soft Int #1 */
MaDevDrv_AddIntFunc( 2, MaDevDrv_SoftInt2 ); /* Soft Int #2 */
MaDevDrv_AddIntFunc( 3, MaDevDrv_SoftInt3 ); /* Soft Int #3 */
MaDevDrv_AddIntFunc( 4, dummy_IntFunc ); /* */
MaDevDrv_AddIntFunc( 5, MaDevDrv_Timer0 ); /* Timer #0 */
MaDevDrv_AddIntFunc( 6, MaDevDrv_Timer1 ); /* Timer #1 */
MaDevDrv_AddIntFunc( 7, MaDevDrv_Fifo ); /* FIFO */
_ma_intstate = 0;
/* Initialize the uninitialized registers by software reset */
MaDevDrv_InitRegisters();
/* Set the PLL. */
MaDevDrv_DeviceControl( 7, MA_ADJUST1_VALUE, MA_ADJUST2_VALUE, 0 );
/* Disable power down mode. */
result = MaDevDrv_PowerManagement( 1 );
if ( result != MASMW_SUCCESS )
{
return result;
}
/* Set volume mode */
MaDevDrv_DeviceControl( 8, 0x03, 0x03, 0x03 );
return MASMW_SUCCESS;
}
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