clkm.h

是一个手机功能的模拟程序

#define CLKM_RELEASELEADRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST &= ~CLKM_LEAD_RST)

/*---------------------------------------------------------------/
/*  CLKM_SETEXTRESET()						*/
/*--------------------------------------------------------------*/
/* Parameters : none						*/
/* Return     :	none						*/
/* Functionality : Set the external reset signal		*/
/*--------------------------------------------------------------*/

#define CLKM_SETEXTRESET ( * (volatile SYS_UWORD16 *) CLKM_CNTL_RST |= CLKM_EXT_RST)

/*---------------------------------------------------------------/
/*  CLKM_CLEAREXTRESET()					*/
/*--------------------------------------------------------------*/
/* Parameters : none						*/
/* Return     :	none						*/
/* Functionality : Clear the external reset signal		*/
/*--------------------------------------------------------------*/

#define CLKM_CLEAREXTRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST &= ~CLKM_EXT_RST)


/*---------------------------------------------------------------/
/*  CLKM_POWERDOWNARM()						*/
/*--------------------------------------------------------------*/
/* Parameters : none						*/
/* Return     :	none						*/
/* Functionality : Power down the ARM mcu			*/
/*--------------------------------------------------------------*/
#define  CLKM_POWERDOWNARM (* (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= ~CLKM_MCLK_EN)

/*---------------------------------------------------------------/
/*  CLKM_SET1P5()						*/
/*--------------------------------------------------------------*/
/* Parameters : none						*/
/* Return     :	none						*/
/* Functionality : Set ARM_MCLK_1P5 bit				*/
/*--------------------------------------------------------------*/

#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
  #define CLKM_SETXP5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK |= CLKM_ARM_MCLK_XP5)
#else
  #define CLKM_SET1P5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK |= 0x0008)
#endif

/*---------------------------------------------------------------/
/*  CLKM_RESET1P5()						*/
/*--------------------------------------------------------------*/
/* Parameters : none						*/
/* Return     :	none						*/
/* Functionality : Reset ARM_MCLK_1P5 bit			*/
/*--------------------------------------------------------------*/

#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
  #define CLKM_RESETXP5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= ~CLKM_ARM_MCLK_XP5)
#else
  #define CLKM_RESET1P5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= 0xfff7)
#endif

/*---------------------------------------------------------------/
/*  CLKM_INITCNTL()						*/
/*--------------------------------------------------------------*/
/* Parameters : value to write in the CNTL register		*/
/* Return     :	none						*/
/* Functionality :Initialize the CLKM Control Clock register	*/
/*--------------------------------------------------------------*/

#define CLKM_INITCNTL(value) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK = value)


#if ((CHIPSET != 4) && (CHIPSET != 7) && (CHIPSET != 8) && (CHIPSET != 10) && (CHIPSET != 11) && (CHIPSET != 12))
  /*---------------------------------------------------------------/
  /*  CLKM_INITLEADPLL()						*/
  /*--------------------------------------------------------------*/
  /* Parameters : value to write in the CNTL_PLL LEAD register	*/
  /* Return     :	none						*/
  /* Functionality :Initialize LEAD PLL control register		*/
  /*--------------------------------------------------------------*/

  #define CLKM_INITLEADPLL(value) (* (volatile SYS_UWORD16 *) CLKM_LEAD_PLL_CNTL = value)
#endif

#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
  /*---------------------------------------------------------------/
  /*  CLKM_DPLL_SWITH_OFF_MODE_CONFIG()                           */
  /*--------------------------------------------------------------*/
  /* Parameters : None                                            */
  /* Return     : none                                            */
  /* Functionality : Configure DPLL switch off mode               */
  /*--------------------------------------------------------------*/

  #define CLKM_DPLL_SWITH_OFF_MODE_CONFIG (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= \
             (CLKM_DPLL_DIS | CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS))
             
  /*---------------------------------------------------------------/
  /*  CLKM_RESET_DPLL_SWITH_OFF_MODE_CONFIG()                     */
  /*--------------------------------------------------------------*/
  /* Parameters : None                                            */
  /* Return     : none                                            */
  /* Functionality : Reset configuration of DPLL switch off mode  */
  /*--------------------------------------------------------------*/
             
  #define CLKM_RESET_DPLL_SWITH_OFF_MODE_CONFIG (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &=\
            ~(CLKM_DPLL_DIS | CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS))

  /*---------------------------------------------------------------/
  /*  CLKM_FORCE_API_HOM_IN_IDLE3()                               */
  /*--------------------------------------------------------------*/
  /* Parameters : None                                            */
  /* Return     : none                                            */
  /* Functionality : SAM/HOM wait-state register force to HOM when*/
  /*                 DSP is in IDLE3 mode                         */
  /*--------------------------------------------------------------*/

  #define CLKM_FORCE_API_HOM_IN_IDLE3 (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_EN_IDLE3_FLG))

  #if (CHIPSET == 4)
    /*---------------------------------------------------------------/
    /*  CLKM_USE_VTCXO_26MHZ()                                      */
    /*--------------------------------------------------------------*/
    /* Parameters : None                                            */
    /* Return     : none                                            */
    /* Functionality : Divide by 2 the clock used by the peripheral */
    /*                 when using external VTCXO at 26 MHz instead  */
    /*                 of 13MHz                                     */
    /*--------------------------------------------------------------*/

    #define CLKM_USE_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_VTCXO_26))

    /*---------------------------------------------------------------/
    /*  CLKM_UNUSED_VTCXO_26MHZ()                                   */
    /*--------------------------------------------------------------*/
    /* Parameters : None                                            */
    /* Return     : none                                            */
    /* Functionality : Use VTCXO=13MHz                              */
    /*--------------------------------------------------------------*/

    #define CLKM_UNUSED_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &= ~(CLKM_VTCXO_26))
  #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
    /*---------------------------------------------------------------/
    /*  CLKM_UNUSED_VTCXO_26MHZ()                                   */
    /*--------------------------------------------------------------*/
    /* Parameters : None                                            */
    /* Return     : none                                            */
    /* Functionality : Use VTCXO=13MHz                              */
    /*--------------------------------------------------------------*/

    #define CLKM_USE_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_VTCXO_2))

    #define CLKM_UNUSED_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &= ~(CLKM_VCLKOUT_2 | CLKM_VTCXO_2))
  #endif


  #define DPLL_SET_PLL_ENABLE (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR |= DPLL_PLL_ENABLE)
  #define DPLL_RESET_PLL_ENABLE (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR &= ~DPLL_PLL_ENABLE)
  
  #define DPLL_INIT_BYPASS_MODE(d_bypass_mode) { \
        *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) &= ~DPLL_BYPASS_DIV; \
        *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) |= (d_bypass_mode << DPLL_BYPASS_DIV_OFFSET); \
       }
    
  #define DPLL_INIT_DPLL_CLOCK(d_pll_div, d_pll_mult) { \
        *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) &= ~(DPLL_PLL_DIV | DPLL_PLL_MULT); \
        *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) |= (d_pll_div << DPLL_PLL_DIV_OFFSET) |\
                                                        (d_pll_mult << DPLL_PLL_MULT_OFFSET); \
       }

  #define DPLL_READ_DPLL_DIV ( ((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_PLL_DIV) >> DPLL_PLL_DIV_OFFSET)
  #define DPLL_READ_DPLL_MUL ( ((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_PLL_MULT)>> DPLL_PLL_MULT_OFFSET)
  #define DPLL_READ_DPLL_LOCK ( (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_LOCK)


#endif

/* ----- Prototypes ----- */

#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
  inline void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div, SYS_UWORD16 clk_xp5);
#else
  inline void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div);
#endif

void wait_ARM_cycles(SYS_UWORD32 cpt_loop);
void initialize_wait_loop(void);
inline SYS_UWORD32 convert_nanosec_to_cycles(SYS_UWORD32 time);