clkm.h

是一个手机功能的模拟程序

/******************************************************************************
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
   product  is  protected  under  copyright  law  and  trade  secret law as an 
   unpublished work.  Created 1987, (C) Copyright 1997 Texas Instruments.  All 
   rights reserved.                                                            
                  
                                                           
   Filename       	: clkm.h

   Description    	: Header file for the CLKM module

   Project        	: drivers

   Author         	: [e-mail]  Patrice Monteil.

   Version number	: 1.10

   Date and time	: 10/23/01 14:34:54

   Previous delta 	: 10/19/01 15:25:25

   SCCS file      	: /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_FRED_CLOCK/drivers1/common/SCCS/s.clkm.h

   Sccs Id  (SID)       : '@(#) clkm.h 1.10 10/23/01 14:34:54 '

 
*****************************************************************************/

#include "chipset.cfg"

#include "sys_types.h"

#define CLKM_ARM_CLK 	MEM_CLKM_ADDR 		/* CLKM ARM CLock Control reg.*/
#define CLKM_MCLK_EN	0x0001 


#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
   #define MASK_CLKIN       0x0006
#endif

#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
  #define CLKM_CLKIN0       0x0002            // Mask to select between DPLL and VTCXO or CLKIN
#else
  #define CLKM_LOW_FRQ	    0x0002            // Mask to select low frequency input CLK_32K 
#endif
#define CLKM_CLKIN_SEL	    0x0004            // Mask to select between VTCXO and CLKIN 

#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
  #define CLKM_ARM_MCLK_XP5 0x0008            // Mask to enable the 1.5 or 2.5 division factor
  #define CLKM_MCLK_DIV     0x0070            // Mask to configure the division factor
#else
  #define MASK_ARM_MCLK_1P5 0x0008            // Mask to enable the 1.5 division factor
  #define CLKM_MCLK_DIV	    0x0030            // Mask to configure the division factor
#endif

#define CLKM_DEEP_PWR	    0x0f00            // Mask to configure deep power
#define CLKM_DEEP_SLEEP	    0x1000            // Mask to configure deep sleep

#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
  #define CLKM_SEL_DPLL     0x0000            // Selection of DPLL for ARM clock generation
  #define CLKM_SEL_VTCXO    0x0001            // Selection of VTCXO for ARM clock generation
  #define CLKM_SEL_CLKIN    0x0003            // Selection of CLKIN for ARM clock generation
  
  #define CLKM_ENABLE_XP5   0x0001            // Enable 1.5 or 2.5 division factor
  #define CLKM_DISABLE_XP5  0x0000            // Disable 1.5 or 2.5 division factor
  
  #define CLKM_ARM_MCLK_DIV_OFFSET 4          // Offset of ARM_MCLK_DIV bits in CNTL_ARM_CLK register
  
  #define CLKM_ARM_CLK_RESET 0x1081           // Reset value of CNTL_ARM_CLK register
#endif

#define CLKM_CNTL_ARM_CLK  (MEM_CLKM_ADDR + 0x00)
#define CLKM_CNTL_CLK	   (MEM_CLKM_ADDR + 2) 	/* CLKM Clock Control reg. */

#define CLKM_IRQ_DIS        0x0001     // IRQ clock is disabled and enabled according to the sleep command
#define CLKM_BRIDGE_DIS	    0x0002     // BRIDGE clock is disabled and enabled according to the sleep command
#define CLKM_TIMER_DIS	    0x0004     // TIMER clock is disabled and enabled according to the sleep command
#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
  #define CLKM_DPLL_DIS     0x0008     // DPLL is set in IDLE when both DSP and ARM are respectively in IDLE3 and sleep mode
#else
  #define CLKM_PLL_SEL	    0x0008     // CLKIN input is connected to the PLL
#endif
#define CLKM_CLKOUT_EN	    0x0010     // Enable CLKOUT(2:0) output clocks
#if (CHIPSET == 4)
  #define CLKM_EN_IDLE3_FLG 0x0020     // DSP idle flag control the API wait state
  #define CLKM_VTCXO_26     0x0040     // VTCXO is divided by 2
#elif (CHIPSET == 6)
  #define CLKM_VTCXO_26     0x0040     // VTCXO is divided by 2
#elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
  #define CLKM_EN_IDLE3_FLG 0x0020     // DSP idle flag control the API wait state
  #define CLKM_VCLKOUT_2    0x0040     // VTCXO is divided by 2
  #define CLKM_VTCXO_2      0x0080     // Input clock to DPLL is divided by 2
#endif

#define CLKM_CNTL_RST 	(MEM_CLKM_ADDR + 4) 	/* CLKM Reset Control reg. */
#define CLKM_LEAD_RST 	0x0002
#define CLKM_EXT_RST 	0x0004

#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
  #define DPLL_LOCK         0x0001     // Mask of DPLL lock status
  #define DPLL_BYPASS_DIV   0x000C     // Mask of bypass mode configuration
  #define DPLL_PLL_ENABLE   0x0010     // Enable DPLL
  #define DPLL_PLL_DIV      0x0060     // Mask of division factor configuration
  #define DPLL_PLL_MULT     0x0F80     // Mask of multiply factor configuration

  #define DPLL_BYPASS_DIV_1 0x00       // Configuration of bypass mode divided by 1
  #define DPLL_BYPASS_DIV_2 0x01       // Configuration of bypass mode divided by 2
  #define DPLL_BYPASS_DIV_4 0x10       // Configuration of bypass mode divided by 4
  
  #define DPLL_BYPASS_DIV_OFFSET 2     // Offset of bypass bits configuration
  #define DPLL_PLL_DIV_OFFSET    5     // Offset of division bits configuration
  #define DPLL_PLL_MULT_OFFSET   7     // Offset of multiply bits configuration
  
  #define DPLL_LOCK_DIV_1   0x0000     // Divide by 1 when DPLL is locked
  #define DPLL_LOCK_DIV_2   0x0001     // Divide by 2 when DPLL is locked
  #define DPLL_LOCK_DIV_3   0x0002     // Divide by 3 when DPLL is locked
  #define DPLL_LOCK_DIV_4   0x0003     // Divide by 4 when DPLL is locked
  
#else
  #define CLKM_LEAD_PLL_CNTL (MEM_CLKM_ADDR + 6)     /* Lead PLL */
  #define CLKM_PLONOFF	0x0001         // PLL enable signal
  #define CLKM_PLMUL	0x001e         // Mask of multiply factor configuration
  #define CLKM_PLLNDIV	0x0020         // PLL or divide mode selection
  #define CLKM_PLDIV	0x0040         // Mask of multiply factor configuration
  #define CLKM_LEAD_PLL_CNTL_MSK 0x00ef // Mask of PLL control register
#endif

#if (CHIPSET == 12)
  #define CLKM_CNTL_CLK_DSP (MEM_CLKM_ADDR + 0x8A) 	/* CLKM CNTL_CLK_REG register */
  
  #define CLKM_NB_DSP_DIV_VALUE   4
  
  #define CLKM_DSP_DIV_1    0x00
  #define CLKM_DSP_DIV_1_5  0x01
  #define CLKM_DSP_DIV_2    0x02
  #define CLKM_DSP_DIV_3    0x03
  
  #define CLKM_DSP_DIV_MASK 0x0003
  
  extern const double dsp_div_value[CLKM_NB_DSP_DIV_VALUE];
  
  /*---------------------------------------------------------------/
  /*  CLKM_DSP_DIV_FACTOR()						*/
  /*--------------------------------------------------------------*/
  /* Parameters : none						*/
  /* Return     :	none						*/
  /* Functionality : Set the DSP division factor			*/
  /*--------------------------------------------------------------*/

  #define CLKM_DSP_DIV_FACTOR(d_dsp_div) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK_DSP = d_dsp_div)


  /*---------------------------------------------------------------/
  /*  CLKM_READ_DSP_DIV()						*/
  /*--------------------------------------------------------------*/
  /* Parameters : none						*/
  /* Return     :	none						*/
  /* Functionality : Read DSP division factor			*/
  /*--------------------------------------------------------------*/

  #define CLKM_READ_DSP_DIV               ((* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK_DSP) & CLKM_DSP_DIV_MASK)
  
  #define CLKM_GET_DSP_DIV_VALUE          dsp_div_value[CLKM_READ_DSP_DIV]

#endif


/*---------------------------------------------------------------/
/*  CLKM_SETLEADRESET()						*/
/*--------------------------------------------------------------*/
/* Parameters : none						*/
/* Return     :	none						*/
/* Functionality : Set the LEAD reset signal			*/
/*--------------------------------------------------------------*/

#define CLKM_SETLEADRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST |= CLKM_LEAD_RST)

/*---------------------------------------------------------------/
/*  CLKM_RELEASELEADRESET()					*/
/*--------------------------------------------------------------*/
/* Parameters : none						*/
/* Return     :	none						*/
/* Functionality : Release the LEAD reset signal		*/
/*--------------------------------------------------------------*/