📄 p_uart.h
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* CCDGEN:WriteStruct_Count==1559
*/
typedef struct
{
U8 device; /*< 0: 1> device number */
U8 dlci; /*< 1: 1> data link connection identifier */
U8 _align0; /*< 2: 1> alignment */
U8 _align1; /*< 3: 1> alignment */
} T_UART_ESCAPE_CNF;
#endif
#ifndef __T_UART_DETECTED_IND__
#define __T_UART_DETECTED_IND__
/*
*
* CCDGEN:WriteStruct_Count==1560
*/
typedef struct
{
U8 device; /*< 0: 1> device number */
U8 dlci; /*< 1: 1> data link connection identifier */
U8 cause; /*< 2: 1> cause of indication */
U8 _align0; /*< 3: 1> alignment */
} T_UART_DETECTED_IND;
#endif
#ifndef __T_UART_ERROR_IND__
#define __T_UART_ERROR_IND__
/*
*
* CCDGEN:WriteStruct_Count==1561
*/
typedef struct
{
U8 device; /*< 0: 1> device number */
U8 dlci; /*< 1: 1> data link connection identifier */
U8 error; /*< 2: 1> error code */
U8 _align0; /*< 3: 1> alignment */
} T_UART_ERROR_IND;
#endif
#ifndef __T_UART_MUX_START_REQ__
#define __T_UART_MUX_START_REQ__
/*
*
* CCDGEN:WriteStruct_Count==1562
*/
typedef struct
{
U8 device; /*< 0: 1> device number */
U8 mode; /*< 1: 1> transparency mechanism */
U8 frame_type; /*< 2: 1> type of frame */
U8 _align0; /*< 3: 1> alignment */
U16 n1; /*< 4: 2> maximum frame size */
U8 t1; /*< 6: 1> acknowledgement timer */
U8 n2; /*< 7: 1> maximum numer of retransmissions */
U8 t2; /*< 8: 1> response timer for the multiplexer control channel */
U8 t3; /*< 9: 1> wake up response timer */
U8 _align1; /*< 10: 1> alignment */
U8 _align2; /*< 11: 1> alignment */
} T_UART_MUX_START_REQ;
#endif
#ifndef __T_UART_MUX_START_CNF__
#define __T_UART_MUX_START_CNF__
/*
*
* CCDGEN:WriteStruct_Count==1563
*/
typedef struct
{
U8 device; /*< 0: 1> device number */
U8 _align0; /*< 1: 1> alignment */
U8 _align1; /*< 2: 1> alignment */
U8 _align2; /*< 3: 1> alignment */
} T_UART_MUX_START_CNF;
#endif
#ifndef __T_UART_MUX_DLC_ESTABLISH_IND__
#define __T_UART_MUX_DLC_ESTABLISH_IND__
/*
*
* CCDGEN:WriteStruct_Count==1564
*/
typedef struct
{
U8 device; /*< 0: 1> device number */
U8 dlci; /*< 1: 1> data link connection identifier */
U8 convergence; /*< 2: 1> convergence layer */
U8 _align0; /*< 3: 1> alignment */
U16 n1; /*< 4: 2> maximum frame size */
U8 service; /*< 6: 1> service on DLC */
U8 _align1; /*< 7: 1> alignment */
} T_UART_MUX_DLC_ESTABLISH_IND;
#endif
#ifndef __T_UART_MUX_DLC_ESTABLISH_RES__
#define __T_UART_MUX_DLC_ESTABLISH_RES__
/*
*
* CCDGEN:WriteStruct_Count==1565
*/
typedef struct
{
U8 device; /*< 0: 1> device number */
U8 dlci; /*< 1: 1> data link connection identifier */
U16 n1; /*< 2: 2> maximum frame size */
} T_UART_MUX_DLC_ESTABLISH_RES;
#endif
#ifndef __T_UART_MUX_DLC_RELEASE_REQ__
#define __T_UART_MUX_DLC_RELEASE_REQ__
/*
*
* CCDGEN:WriteStruct_Count==1566
*/
typedef struct
{
U8 device; /*< 0: 1> device number */
U8 dlci; /*< 1: 1> data link connection identifier */
U8 _align0; /*< 2: 1> alignment */
U8 _align1; /*< 3: 1> alignment */
} T_UART_MUX_DLC_RELEASE_REQ;
#endif
#ifndef __T_UART_MUX_DLC_RELEASE_IND__
#define __T_UART_MUX_DLC_RELEASE_IND__
/*
*
* CCDGEN:WriteStruct_Count==1567
*/
typedef struct
{
U8 device; /*< 0: 1> device number */
U8 dlci; /*< 1: 1> data link connection identifier */
U8 _align0; /*< 2: 1> alignment */
U8 _align1; /*< 3: 1> alignment */
} T_UART_MUX_DLC_RELEASE_IND;
#endif
#ifndef __T_UART_MUX_SLEEP_REQ__
#define __T_UART_MUX_SLEEP_REQ__
/*
*
* CCDGEN:WriteStruct_Count==1568
*/
typedef struct
{
U8 device; /*< 0: 1> device number */
U8 _align0; /*< 1: 1> alignment */
U8 _align1; /*< 2: 1> alignment */
U8 _align2; /*< 3: 1> alignment */
} T_UART_MUX_SLEEP_REQ;
#endif
#ifndef __T_UART_MUX_SLEEP_IND__
#define __T_UART_MUX_SLEEP_IND__
/*
*
* CCDGEN:WriteStruct_Count==1569
*/
typedef struct
{
U8 device; /*< 0: 1> device number */
U8 _align0; /*< 1: 1> alignment */
U8 _align1; /*< 2: 1> alignment */
U8 _align2; /*< 3: 1> alignment */
} T_UART_MUX_SLEEP_IND;
#endif
#ifndef __T_UART_MUX_WAKEUP_REQ__
#define __T_UART_MUX_WAKEUP_REQ__
/*
*
* CCDGEN:WriteStruct_Count==1570
*/
typedef struct
{
U8 device; /*< 0: 1> device number */
U8 _align0; /*< 1: 1> alignment */
U8 _align1; /*< 2: 1> alignment */
U8 _align2; /*< 3: 1> alignment */
} T_UART_MUX_WAKEUP_REQ;
#endif
#ifndef __T_UART_MUX_WAKEUP_IND__
#define __T_UART_MUX_WAKEUP_IND__
/*
*
* CCDGEN:WriteStruct_Count==1571
*/
typedef struct
{
U8 device; /*< 0: 1> device number */
U8 _align0; /*< 1: 1> alignment */
U8 _align1; /*< 2: 1> alignment */
U8 _align2; /*< 3: 1> alignment */
} T_UART_MUX_WAKEUP_IND;
#endif
#ifndef __T_UART_MUX_CLOSE_REQ__
#define __T_UART_MUX_CLOSE_REQ__
/*
*
* CCDGEN:WriteStruct_Count==1572
*/
typedef struct
{
U8 device; /*< 0: 1> device number */
U8 _align0; /*< 1: 1> alignment */
U8 _align1; /*< 2: 1> alignment */
U8 _align2; /*< 3: 1> alignment */
} T_UART_MUX_CLOSE_REQ;
#endif
#ifndef __T_UART_MUX_CLOSE_IND__
#define __T_UART_MUX_CLOSE_IND__
/*
*
* CCDGEN:WriteStruct_Count==1573
*/
typedef struct
{
U8 device; /*< 0: 1> device number */
U8 _align0; /*< 1: 1> alignment */
U8 _align1; /*< 2: 1> alignment */
U8 _align2; /*< 3: 1> alignment */
} T_UART_MUX_CLOSE_IND;
#endif
#ifndef __T_UART_DRIVER_SENT_IND__
#define __T_UART_DRIVER_SENT_IND__
/*
*
* CCDGEN:WriteStruct_Count==1574
*/
typedef struct
{
U8 dummy; /*< 0: 1> no parameters */
} T_UART_DRIVER_SENT_IND;
#endif
#ifndef __T_UART_DRIVER_RECEIVED_IND__
#define __T_UART_DRIVER_RECEIVED_IND__
/*
*
* CCDGEN:WriteStruct_Count==1575
*/
typedef struct
{
U8 dummy; /*< 0: 1> no parameters */
} T_UART_DRIVER_RECEIVED_IND;
#endif
#ifndef __T_UART_DRIVER_FLUSHED_IND__
#define __T_UART_DRIVER_FLUSHED_IND__
/*
*
* CCDGEN:WriteStruct_Count==1576
*/
typedef struct
{
U8 dummy; /*< 0: 1> no parameters */
} T_UART_DRIVER_FLUSHED_IND;
#endif
#include "CDG_LEAVE.h"
#endif
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