mmiutilapi.c

是一个手机功能的模拟程序

/*
 * Description:
 *		This module contains utilities API for MMI development.
 *
 * Histroy:
 *		2003/11/20	Talcon created.
 *		2004/07/06	robert.chen 
 *			add dynamic memory manager API for MMI
 *			add trace API to log message in internal RAM
 */ 
#ifndef _MMIUTILAPI_C_
#define _MMIUTILAPI_C_

#include "nucleus.h"

#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include "mmiutilapi.h"
#include "rvf_api.h"

//#define TDTRACE 1
//#if TDTRACE
#define _TARGET
//#define RT_TRACE

#ifndef _INNOVATION_EMULATOR_
#pragma DATA_SECTION (mmi_dbgBuf, ".MMITR_BUF");
#endif
static char mmi_dbgBuf[MMI_DBGBUF_SZ];

#ifndef _INNOVATION_EMULATOR_
	static NU_SEMAPHORE mmimemSem;
	static NU_MEMORY_POOL mmimemPool;
#endif

#if (MMIMEM_INFORMATION == 1)
	static T_MMIMEM_INFO mmi_memInfo;
	static unsigned int	totalAlloc = 0;
#endif

#if (MMIMEM_TRACE == 1) 
	#define MMIMEMTRACE_MSG(msg) MI_dbgPrintf msg
#else
	#define MMIMEMTRACE_MSG(msg)
#endif

/**
 *	Output printf-like formated string to rivieratracer.
 */
#ifndef RT_TRACE 
void MI_dbgPrintf(const char* const format, ...)
{

	va_list pArgs;
	if(format == NULL) //modified by xie 04-07-22 for avoiding print NULL string.
	{
	#ifdef _TARGET
	    rvf_send_trace("occur NULL string in Trace!!!!",strlen("occur NULL string in Trace!!!!"), NULL_PARAM, RV_TRACE_LEVEL_DEBUG_HIGH, 0);
	#endif
		return;
	}
	//return;/*2004/04/01,talcon add for disable trace*/
	va_start(pArgs, format);
	vsprintf(mmi_dbgBuf, format, pArgs);
#ifdef _TARGET
	rvf_send_trace(mmi_dbgBuf, strlen(mmi_dbgBuf), NULL_PARAM, RV_TRACE_LEVEL_DEBUG_HIGH, 0);
#else
	printf(mmi_dbgBuf);
#endif
	va_end(pArgs);
}
#else
#define MEM_UART_MODEM  (0xFFFF5800)
#define MEM_UART_IRDA   (0xFFFF5000)
/*
 * 16750 addresses. Registers accessed when LCR[7] = 0.
 */

#define RHR (0x00) /* Rx buffer register - Read access   */
#define THR (0x00) /* Tx holding register - Write access */
#define IER (0x01) /* Interrupt enable register          */



/*
 * 16750 addresses. Bit 5 of the FCR register is accessed when LCR[7] = 1.
 */

#define IIR  (0x02) /* Interrupt ident. register - Read only */
#define FCR  (0x02) /* FIFO control register - Write only    */
#define LCR  (0x03) /* Line control register                 */
#define MCR  (0x04) /* Modem control register                */
#define LSR  (0x05) /* Line status register                  */
#define MSR  (0x06) /* Modem status register                 */
#define TCR  (0x06) /* Transmission control register         */
#define TLR  (0x07) /* Trigger level register                */
#define MDR1 (0x08) /* Mode definition register 1            */
#define SCR  (0x10) /* Supplementary Control register        */
#define SSR  (0x11) /* Supplementary Status register         */

/*
 * Line status register.
 */

#define DR   (0x01) /* Data ready                                  */
#define OE   (0x02) /* Overrun error                               */
#define PE   (0x04) /* Parity error                                */
#define FE   (0x08) /* Framing error                               */
#define BI   (0x10) /* Break interrupt                             */
#define THRE (0x20) /* Transmitter holding register (FIFO empty)   */
#define TEMT (0x40) /* Transmitter empty (FIFO and TSR both empty) */


/*
 * Mode definition register 1.
 */

#define UART_MODE             (0x00)
#define SIR_MODE              (0x01)
#define UART_MODE_AUTOBAUDING (0x02) /* Reserved in UART/IrDA. */
#define RESET_DEFAULT_STATE   (0x07)
#define IR_SLEEP_DISABLED     (0x00)
#define IR_SLEEP_ENABLED      (0x08)
#define SIR_TX_WITHOUT_ACREG2 (0x00) /* Reserved in UART/modem. */
#define SIR_TX_WITH_ACREG2    (0x20) /* Reserved in UART/modem. */
#define FRAME_LENGTH_METHOD   (0x00) /* Reserved in UART/modem. */
#define EOT_BIT_METHOD        (0x80) /* Reserved in UART/modem. */


/*
 * EFR is accessed when LCR[7:0] = 0xBF.
 */

#define EFR (0x02) /* Enhanced feature register */


/*
 * Enhanced feature register.
 */
 
#define ENHANCED_FEATURE_BIT (4) /* Use RESET_BIT and SET_BIT macros. */


/*
 * FIFO control register.
 */

#define FIFO_ENABLE   (0x01)
#define RX_FIFO_RESET (0x02)
#define TX_FIFO_RESET (0x04)


/*
 * 16750 addresses. Registers accessed when LCR[7] = 1.
 */

#define DLL (0x00) /* Divisor latch (LSB) */
#define DLM (0x01) /* Divisor latch (MSB) */

/*
 * Line control register.
 */

#define WLS_5         (0x00) /* Word length: 5 bits                    */
#define WLS_6         (0x01) /* Word length: 6 bits                    */
#define WLS_7         (0x02) /* Word length: 7 bits                    */
#define WLS_8         (0x03) /* Word length: 8 bits                    */
#define STB           (0x04) /* Number of stop bits: 0: 1, 1: 1,5 or 2 */
#define PEN           (0x08) /* Parity enable                          */
#define EPS           (0x10) /* Even parity select                     */
#define BREAK_CONTROL (0x40) /* Enable a break condition               */
#define DLAB          (0x80) /* Divisor latch access bit               */
#define DIV_EN_BIT    (7)

/*
 * Modem control register.
 */

#define MDTR (0x01) /* Data terminal ready. */
#define MRTS (0x02) /* Request to send.     */
#define TCR_TLR_BIT (6)

/*
 * TLR is used to program the RX FIFO trigger levels. FCR[7:4] are  not used.
 */
 
#define RX_FIFO_TRIGGER_LEVEL (12 << 4)


#define UART_UIR	(0xFFFF6000)	   /* UART Interface Register */


/*
 * UART_UIR bit definitions.
 */
#define UART_ACCESS		(0)
#define UART_MASK_IT	(1)


#define IER_SLEEP (0x10)  



#define WRITE_UART_REGISTER(REG,VALUE) \
            *((volatile unsigned char *) (MEM_UART_IRDA + (REG))) = (VALUE)

#define READ_UART_REGISTER(REG) \
            *((volatile unsigned char *) (MEM_UART_IRDA + (REG)))

#define WRITE_UART1_REGISTER(REG,VALUE) \
            *((volatile unsigned char *) (MEM_UART_MODEM + (REG))) = (VALUE)

#define READ_UART1_REGISTER(REG) \
            *((volatile unsigned char *) (MEM_UART_MODEM + (REG)))


#define RESET_BIT(REG,BIT)    \
			(WRITE_UART_REGISTER ( \
			      REG, READ_UART_REGISTER ( REG) & ~(1 << (BIT))))

#define SET_BIT(REG,BIT)      \
			(WRITE_UART_REGISTER ( \
			      REG, READ_UART_REGISTER ( REG) | (1 << (BIT))))




char head[] = "\x02\x11\x00\x00\x00\x00\x03";
void Uart_Send_String(char *p)
{
int	i;
    WRITE_UART_REGISTER (IER, 0x00);
	
	while(!(READ_UART_REGISTER ( LSR) & THRE));
	
	for(i=0; i<7; i++)
		WRITE_UART_REGISTER ( THR, head[i]);

	while(*(p)) 
	{
		while(!(READ_UART_REGISTER ( LSR) & THRE));

		if (READ_UART_REGISTER ( LSR) & THRE) 
		{
	       	WRITE_UART_REGISTER ( THR, *p++);
	    }
	}

	while(!(READ_UART_REGISTER ( LSR) & THRE));
	WRITE_UART_REGISTER ( THR, 0x02);
}

void MI_dbgPrintf(const char* const format, ...)
{

	va_list pArgs;
	//return;/*2004/04/01,talcon add for disable trace*/
	va_start(pArgs, format);
	vsprintf(mmi_dbgBuf, format, pArgs);
#ifndef _INNOVATION_EMULATOR_
	Uart_Send_String(mmi_dbgBuf);
#else
	printf(mmi_dbgBuf);
#endif
	va_end(pArgs);
}
#endif
/***
 *	Initialize MMI memory manager.
 */
int MI_mmimem_Init(void)
{
	int i, j;
	T_MMIMEM_PCB *pPCB;
	T_MMIMEM_PMHDR	*pPMH;

#ifndef _INNOVATION_EMULATOR_
	i = NU_Create_Semaphore(&mmimemSem, "s", 1, NU_FIFO);
	MMIMEMTRACE_MSG(("MI_mmimem_Init():Create Sema, ret=%d", i));
	if(i != NU_SUCCESS)
		return EC_MMIMEM_ERROR;	

	/* init dynamic memory management */
	i = NU_Create_Memory_Pool(&mmimemPool, "p", mmiDynMemCB.pStartAddr, mmiDynMemCB.poolSize, MMI_DYNMEM_BLKSZ, NU_FIFO);
	MMIMEMTRACE_MSG(("MI_mmimem_Init():Create dyn mem, ret=%d", i));
	if(i != NU_SUCCESS)
		return EC_MMIMEM_ERROR;	
#endif
	

	/* init partition memory management */	
	for(i = 0; i < MMI_PARTMEM_POOL_NUM; i ++)
	{	
		pPCB = &mmiPCBTbl[i];
		j	 = 1;		
		pPMH = (T_MMIMEM_PMHDR*)pPCB->pStartAddr;
		pPCB->pFree = pPMH;
		
		while(j <= pPCB->totalNum)
		{
			pPMH->pPCB = pPCB;			
			pPMH->next = (T_MMIMEM_PMHDR*)((unsigned char*)pPCB->pStartAddr + (j * (PM_HEADER_LEN + pPCB->partSize)));
			
		#if (MMIMEM_MONITOR == 1)
			memset((void*)pPMH->caller, 0, MMIMEM_CALLER_LEN);
			pPMH->line = 0;	
		#endif
			
			if(j == pPCB->totalNum)
				pPMH->next = NULL;
			else
				pPMH = pPMH->next;

			j ++;	
		}		
	}

#if (MMIMEM_INFORMATION == 1)
	memset((void*)&mmi_memInfo, 0, sizeof(T_MMIMEM_INFO));
	mmi_memInfo.min_reqsz = 0xffffffff;
#endif	

	return EC_MMIMEM_OK;
}


/***
 * Allocate a memory block, if success, return EC_MMIMEM_OK,
 * otherwise return a negative number indicating the reason.
 */
#if (MMIMEM_MONITOR == 1)
EXTERN_LCL int MI_mmimem_Alloc(void **buf, unsigned int size, char *name, int line)
#else
EXTERN_LCL int MI_mmimem_Alloc(void **buf, unsigned int size)
#endif
{
	int i;
	STATUS ret, error = EC_MMIMEM_ERROR;	
	T_MMIMEM_PMHDR *pPMH;
	T_MMIMEM_DMHDR *pDMH;
#if (MMIMEM_MONITOR == 1)
	char *file;
#endif
#if (MMIMEM_UNBLKFREE == 1)
	T_MMIMEM_PMHDR *pPrePMH;
	T_MMIMEM_DMHDR *pPreDMH;
#endif

#if (MMIMEM_MONITOR == 1)
  #ifndef _INNOVATION_EMULATOR_
	file = strrchr(name, '/');
  #else
  	file = strrchr(name, '\\');
  #endif
	if(file)
		file++;		
	MMIMEMTRACE_MSG(("MI_mmimem_Alloc():%d, %d, %s, %d", (UINT32)buf, size, file, line));
#else
	MMIMEMTRACE_MSG(("MI_mmimem_Alloc():%d, %d", (UINT32)buf, size));;
#endif

	if(buf == NULL || size == 0)
	{
		MMIMEMTRACE_MSG(("MI_mmimem_Alloc():para err!"));		
		return error;
	}
	*buf = NULL;
	
#ifndef _INNOVATION_EMULATOR_
	ret = NU_Obtain_Semaphore(&mmimemSem, 20);
	if(ret != NU_SUCCESS)
	{
		MMIMEMTRACE_MSG(("MI_mmimem_Alloc():obtain sema err,ret=%d", ret));
		return error;
	}
#endif

#if (MMIMEM_INFORMATION == 1)
	if(mmi_memInfo.min_reqsz > size)
		mmi_memInfo.min_reqsz = size;
	else if(mmi_memInfo.max_reqsz < size)
		mmi_memInfo.max_reqsz = size;
#endif

	/* allocate from memory pool if possible */
	for(i = 0; i < MMI_PARTMEM_POOL_NUM; i ++)
	{
		if(size <= mmiPCBTbl[i].partSize)
		{		
		#if (MMIMEM_UNBLKFREE == 1)
		 	pPMH	= mmiPCBTbl[i].pAllocated;
		 	pPrePMH = NULL;
		 	
		 	while(pPMH)
		 	{
		 		if(pPMH->inuse == MMI_MEMINUSE_FLAG)
		 		{
		 			pPrePMH = pPMH;
		 			pPMH 	= pPMH->next;
		 		}
		 		else
		 		{
		 			break;
		 		}
		 	}

			if(pPMH != NULL)
			{
				if(pPrePMH == NULL)
				{
					mmiPCBTbl[i].pAllocated = pPMH->next;					
				}
				else