fputest.c

操作系统SunOS 4.1.3版本的源码

}
         
/*
 *      The following routine tests with the patttern given
 */
registers_one()
{
        int     i,j, result;

        for (i = 0; i < 32; i++) {
                for (j = 0; j < 5; j++) {
                        result = register_test(i, pat[j]);
                        if (result != pat[j]) {
                          send_message(0, ERROR, "\nregister read/write failed : reg = %d, expected / observed = %x / %x\n",
                                        i, pat[j], result);
                         return(-1);
                        }
                }
        }
        return(0);
}  
         
/*
 * Function: 	Check the integrity of the FPU status register
 * 		by writing patterns and reading them back.
 *
 * History:	Updated to add FPU_ID_MASK (bds) so that the FPU ID
 *		is ignored. (Weitek = 00, TI = 01)
 *		6/2/89.  Changed FPU_ID_MASK to 0xFFF97FFF to accomodate
 *		campus.
 * History:	Updated FPU_ID_MASK to work with the LSI804 chip ----
 *		---- aka "Meiko" FPU -------- 1/7/91. 
 *
 * History:	Updated FPU_ID_MASK to ignore the unused bits 29,28 and 12.
 *
 * History:     Updated FPU_ID_MASK to ignore the ftt bits 14-16.
 *
 */

#define FPU_ID_MASK  0xCFF02FFF

static u_long fsr_testdata[] =
		{ 
			0x08000000,
	  		0x40000000,
			0x48000000,
			0x80000000,
			0x88000000,
			0xC0000000,
			0xC8000000
	  	};

fsr_test()
{
        int i;
        u_long result;

        for (i = 0; i < 7; i++) {  
                set_fsr(fsr_testdata[i]);
                result = (get_fsr() & FPU_ID_MASK);
                if (result != fsr_testdata[i]) {
                        send_message(0, ERROR, "\nFSR Error: expected / observed = %x / %x",
				 fsr_testdata[i], result);
			if ((result & 0x0001c000) != 0)
				ftt_decode(result);
                        return(-1);
                }
        }
        return(0);
}

psr_test()
{
        unsigned long testdata,result;

        printf("        PSR FPU bit Test:");
         
        if (result & 0x01000) {
                printf("\nFPU bit is disabled in the PSR, Check whether the FPU is placed correctly.\n");    
                return(-1);    
        }
        printf(" Passed.\n");
        return(0);
}

/*
 *	wstatus.c
 * This test causes the Weitek chips to produce every possible
 * value at the S+ outputs.  These bits are then observed via
 * the WSTATUS register.  The ALU and multiplier are distinguished 
 * by the instruction address
 */
fpu_ws()
{
        int     operation;
        unsigned long i, cmp_status, tmp_var, amsw, alsw, bmsw, blsw;
        unsigned long *ptr, status;
        unsigned long actual; 
        unsigned long tmp_val;



        set_fsr(0x0);
        donot_dq = 0;
        status = get_fsr();
        status = status | 0xF000000;
        set_fsr(status);
        error_ok = 1;

        for (i = 0; test_ws[i].instr != 0; i++) {

                trap_flag = 0x0;                /* unset the flag */     
                amsw = test_ws[i].a_msw;        /* get the most sig. word */
                alsw = test_ws[i].a_lsw;        /* get the least "      "  */
                bmsw = test_ws[i].b_msw;
                blsw = test_ws[i].b_lsw;
                operation = test_ws[i].instr;
                switch (operation) {

                        case 1 :
                                wadd_sp(amsw ,bmsw);
                                break;
                        case 2 :
                                wadd_dp(amsw, alsw, bmsw, blsw);
                                break;
                        case 3 :
                                wdiv_sp(amsw, bmsw);
                                break;
                        case 4 :
                                wdiv_dp(amsw, alsw, bmsw, blsw); 
                                break; 
                        case 5 :
                                wmult_sp(amsw, bmsw); 
                                break; 
                        case 6 :
                                wmult_dp(amsw, alsw, bmsw, blsw);  
                                break;  
                        default:
                                send_message(0, ERROR, "\nWrong code is given.\n");
                                break;
                }
                if (i) {
                    if (!trap_flag) {
                        send_message(0, ERROR, " FPU Trap did not occur , i = %d.\n", i);
#ifdef STOPONERROR
                                return(-1);
#endif
                    }
                }
                else {
                    if (trap_flag) {
                        send_message(0, ERROR, " FPU Trap Should not occur but occured.\n");
#ifdef STOPONERROR
                               return(-1);
#endif
                    }
                } 
                status = fsr_at_trap & 0x0001c000;
/*
 *  Second level:  Confirm that the ftt bits in the FSR are set correctly
 *                 *** Note this is not valid with SunOs >= 4.0 because
 *                 the OS clears the FSR on an exception.
 */
/*DISABLED - BDS
 *
 *                if (i) {
 *		if (((fsr_at_trap & 0xc000) >> 12) != test_ws[i].status) {
 *			printf("\nDid not create an correct exception, ");
 *			printf("ftt = %x should be = %x\n",
 *			     (fsr_at_trap & 0x1c000) >> 12, test_ws[i].status);
 *			ftt_decode(fsr_at_trap);
 *                       switch (operation) {
 *
 *                               case 1 : printf(" single precision add :");
 *                                       break;
 *                              case 2 :
 *                                      printf(" double precision add :");
 *                                      break;
 *                              case 3 :
 *                                      printf(" single precision divide :");
 *                                      break;
 *                              case 4  :
 *                                      printf(" double precision divide :");
 *                                      break;
 *                              case 5 :
 *                                      printf(" single precision multiply :");
 *                                      break;
 *                              case 6  :
 *                                      printf(" double precision multiply :");
 *                                      break;
 *                      }
 *                      if ((operation == 1) || (operation == 3) ||
 *					        (operation ==5))
 *                              printf("A = %x, B = %x\n",
 *					test_ws[i].a_msw, test_ws[i].b_msw);
 *                      else 
 *                              printf("Amsw = %x, Alsw = %x, Bmsw = %x, Blsw = %x\n",
 *                              	test_ws[i].a_msw, test_ws[i].a_lsw,
 *					test_ws[i].b_msw, test_ws[i].b_lsw);
 * #ifdef STOPONERROR
 *                      return(-1);
 * #endif
 *                }
 *              }
 *              if (i < 4) {
 *                      if (i == 1) 
 *                      if (!(fsr_at_trap & 0x2)) { 
 *                              printf("\nDid not create correct IEEE exception (Divide By zero) : expected = 2, observed = %x\n",
 *					 fsr_at_trap & 0x1f);  
 *					ftt_decode(fsr_at_trap);
 * #ifdef STOPONERROR
 *                                      return(-1); 
 * #endif
 *                      }
 *                      if (i == 2) 
 *                      if (!(fsr_at_trap & 0x8)) { 
 *                              printf("\nDid not create correct IEEE exception (Overflow) : expected = 8, observed = %x\n", fsr_at_trap & 0x1f);    
 *					ftt_decode(fsr_at_trap);
 * #ifdef STOPONERROR
 *					return(-1); 
 * #endif
 *                      } 
 *                      if (i == 3) 
 *                      if (!(fsr_at_trap & 0x10))  {
 *                              printf("\nDid not create correct IEEE exception (Invalid) : expected = 10, observed = %x\n", fsr_at_trap & 0x1f); 
 *					ftt_decode(fsr_at_trap);
 *					return(-1);  
 *                      }
 *              } 
 ***** END of Disabled Section */
        }
        error_ok = 0;
        return(0);
}

fpu_ws_nxm()
{
	int           operation;
        unsigned long i, cmp_status, tmp_var, amsw, alsw, bmsw, blsw;
        unsigned long *ptr, status;
        unsigned long prev_status;
        unsigned long actual;
        unsigned long tmp_val;

        prev_status = get_fsr();
        status = prev_status | 0xF800000;
        set_fsr(status);
        donot_dq = 0;
        error_ok = 1;

        for (i = 0; test_ws[i].instr != 0; i++) {
         
                trap_flag = 0x0;                /* unset the trap flag */
                amsw = test_ws[i].a_msw;        /* get most significant word */
                alsw = test_ws[i].a_lsw;        /* get the least "      "  */
                bmsw = test_ws[i].b_msw;
                blsw = test_ws[i].b_lsw;
                operation = test_ws[i].instr;
                switch (operation) {

                        case 1 :
                                wadd_sp(amsw ,bmsw);
                                break;
                        case 2 :
                                wadd_dp(amsw, alsw, bmsw, blsw);
                                break;
                        case 3 :
                                wdiv_sp(amsw, bmsw);
                                break;
                        case 4 :
                                wdiv_dp(amsw, alsw, bmsw, blsw); 
                                break; 
                        case 5 :
                                wmult_sp(amsw, bmsw); 
                                break; 
                        case 6 :
                                wmult_dp(amsw, alsw, bmsw, blsw);  
                                break;  
                        default:
                                printf("\nWrong code is given.\n");
                                break;
                }
                if (!trap_flag) {
                        send_message(0, ERROR, "Bus Error did not occur.\n");
                        return(-1);
                }
                status = fsr_at_trap & 0x1c000;
/*
 *  Second level:  Confirm that the ftt bits in the FSR are set correctly
 *                 *** Note this is not valid with SunOs >= 4.0 because
 *                 the OS clears the FSR on an exception.
 */
/*DISABLED - BDS
 *
 *		if (((fsr_at_trap & 0xc000) >> 12) != test_ws[i].status) {
 *			printf("\nDid not create an correct exception, ");
 *			printf("ftt = %x should be = %x\n",
 *			     (fsr_at_trap & 0x1c000) >> 12, test_ws[i].status);
 *
  *                       switch (operation) { 
 * 
 *                                case 1 : printf(" single precision add :");
 *                                        break;
 *                                case 2 : 
 *                                        printf(" double precision add :"); 
 *                                        break; 
 *                                case 3 :
 *                                        printf(" single precision divide :");
 *                                        break;  
 *                                case 4  :  
 *                                        printf(" double precision divide :"); 
 *                                        break;   
 *                                case 5 : 
 *                                        printf(" single precision multiply :"); 
 *                                        break;   
 *                                case 6  :   
 *                                        printf(" double precision multiply :");
 *                                        break;
 *                        } 
 *                        if ((operation == 1) || (operation == 3) || (operation ==5))
 *                                printf("A = %x, B = %x\n", test_ws[i].a_msw, test_ws[i].b_msw);
 *                        else
 *                                printf("Amsw = %x, Alsw = %x, Bmsw = %x, Blsw = %x\n",
 *                                test_ws[i].a_msw, test_ws[i].a_lsw, test_ws[i].b_msw, test_ws[i].b_lsw);         
 *#ifdef STOPONERROR
 *                        return(-1); 
 *#endif
 *
 *                }
 ********* End of Disabled CODE BDS  */

                if (i < 4) {
                        if (i == 0) 
                        if (!(fsr_at_trap & 0x1)) {
                                send_message(0, ERROR, "\nDid not create correct IEEE exception (Inexact): expected = 1, observed = %x\n", fsr_at_trap & 0x1f); 
#ifdef STOPONERROR
                                        return(-1);
#endif
                        }
                        if (i == 1) 
                        if (!(fsr_at_trap & 0x2)) { 
                                send_message(0, ERROR, "\nDid not create correct IEEE exception (Divide By zero) : expected = 2, observed = %x\n", fsr_at_trap & 0x1f);  
#ifdef STOPONERROR
                                        return(-1); 
#endif
                        }
                        if (i == 2) 
                        if (!(fsr_at_trap & 0x8)) { 
                                send_message(0, ERROR, "\nDid not create correct IEEE exception (Overflow) : expected = 8, observed = %x\n", fsr_at_trap & 0x1f);    
#ifdef STOPONERROR
                                        return(-1); 
#endif
                        } 
                        if (i == 3) 
                        if (!(fsr_at_trap & 0x10)) {
                                send_message(0, ERROR, "\nDid not create correct IEEE exception (Invalid) : expected = 10, observed = %x\n", fsr_at_trap & 0x1f); 
#ifdef STOPONERROR
                                        return(-1);  
#endif
                        }
                } 
         
        }
        error_ok = 0;
        clear_regs(0);
        set_fsr(prev_status);
        return(0);
}

/*
 * 	winitfp.c
 */
#ifdef SVR4
void	sigsegv_handler( int sig, siginfo_t *sip, ucontext_t *ucp)
#else SVR4
void	sigsegv_handler( sig, code, scp)
int sig, code ;
struct sigcontext *scp ;
#endif SVR4
{
#ifdef SVR4
	ucp->uc_mcontext.fpregs.fpu_qcnt = 0;
        fsr_at_trap = get_fsr();
        trap_flag = 0x1;
        if (error_ok)