fputest.c

操作系统SunOS 4.1.3版本的源码

/*
 *static char     frefsccsid[] = "@(#)fputest.c 1.1 7/30/92 Copyright Sun Microsystems";
 */
#include <sys/types.h>
#include <sys/file.h>
#include <signal.h>
#ifdef SVR4
#include <siginfo.h>
#include <ucontext.h>
#include <sys/machsig.h>
#endif SVR4
#include <stdio.h>
#include <sys/time.h>
#include <sys/ioctl.h>
#include <errno.h>
#include "sdrtns.h"

#define SYSTEST_ERROR		6

/* ================ Note on BDS Modifications Made on 7/12/88 ================
 *
 * The second level testing of "forced exceptions" is disabled in this version
 * for the following reasons:
 *
 * From dock@trinity Thu Jul  7 10:47:46 1988
 * To: bskreen@bienhoa
 * Subject: Re:  SunOS differences related to fpurel and fputest (sysdiag)
 * Cc: dgh@trinity
 *
 * The ftt bits should not be tested in a user level program diagnostic.
 * The kernel in 4.0 clears the bits and in 3.2 it left them as they were.
 * A stand alone diagnostic that runs in system mode is the appropriate
 * place for this check.  I suggest deleting the check of the ftt.
 * -dock
 *
 *  The ftt testing (confirming the reason for the exception) can be enabled
 *  on SunOS 3.2 in the future <highly recommended>. BDS
 *
 */



/*
 * 	main.c
 */
char *err_msg[] = {
	"",       
        "FSR Register Test",
        "Registers Test",
        "Nack Test",
        "Move Registers Test",
        "Negate: Positive to Negative Test",
        "Negate: Negative to Positive Test",
        "Absolute Test",
        "Integer to Floating Point: Single Precision Test",
        "Integer to Floating Point: Double Precision Test",
        "Floating to Integer: Single Precision Test",
        "Floating to Integer: Double Precision Test",
        "Single to Integer Round Toward Zero Test",
        "Double to Integer Round Toward Zero Test",
        "Format Conversion: Single to Double Test",
        "Format Conversion: Double to Single Test",
        "Addition: Single Precision Test",
        "Addition: Double Precision Test",
        "Subtraction: Single Precision Test",
        "Subtraction: Double Precision Test",
        "Multiply: Single Precision Test",
        "Multiply: Double Precision Test",
        "Division: Single Precision Test",
        "Division: Double Precision Test",
        "Compare: Single Precision Test",
        "Compare: Double Precision Test",
        "Compare And Exception If Unordered: Single Precision Test",
        "Compare And Exception If Unordered: Double Precision Test",
        "Branching On Condition Instructions Test",
        "No Branching on Condition Instructions Test",
        "Chaining (Single Precision) Test",
        "Chaining (Double Precision) Test",
        "FPP Status Test",
        "FPP Status (NXM=1) Test",
        "Lock Test",
        "Datapath (Single Precision) Test",
        "Datapath (Double Precision) Test",
        "Load Test",
        "Linpack Test"
}; 



int     sig_err_flag;
u_long  contexts; /* to get the context in case it fails */
int	donot_dq;
unsigned long error_ok;
unsigned long   fsr_at_trap;
unsigned long   trap_flag;
#ifdef SVR4
sigset_t     restore_samask;
int     restore_saonstack;
void    (*restore_sahandler)();
sigset_t     res_seg_samask;
int     res_seg_saonstack;
void    (*res_seg_sahandler)();
void    sigsegv_handler(int, siginfo_t *, ucontext_t *);
void    sigfpe_handler(int, siginfo_t *, ucontext_t *);
struct sigaction newfpu, oldfpu, oldseg, newseg;
#else SVR4
int     restore_svmask;
int     restore_svonstack;
void	(*restore_svhandler)();
int     res_seg_svmask;
int     res_seg_svonstack;
void	(*res_seg_svhandler)();
struct sigvec newfpu, oldfpu, oldseg, newseg;
#endif SVR4

extern 	int 	errno ;
extern  int	check_fpu();
extern	int	debug;
extern	int	simulate_error;
extern	char	*msg;

/*
 *	wstatus.c
 */
#define    zero_sp    0x00000000
#define    zero_msw   0x00000000
#define    zero_lsw   0x00000000

#define    half_sp    0x3f000000
#define    half_msw   0x3fe00000
#define    half_lsw   0x00000000

#define    one_sp    0x3f800000
#define    one_msw    0x3ff00000
#define    one_lsw    0x00000000

#define    two_sp    0x40000000
#define    two_msw   0x40000000
#define    two_lsw   0x00000000

#define    pi_sp    0x40490fdb
#define    pi_msw   0x400921fb
#define    pi_lsw   0x54442d18

#define    pi_4_sp  0x3f490fdb
#define    pi_4_msw 0x3fe921fb
#define    pi_4_lsw 0x54442d18

#define    inf_sp   0x7f800000
#define    inf_msw  0x7ff00000
#define    inf_lsw  0x00000000

#define    nan_sp   0x7fbfffff
#define    nan_msw  0x7ff7ffff
#define    nan_lsw  0xffffffff

#define    denorm_sp    0x00000001
#define    denorm_msw   0x00000000
#define    denorm_lsw   0x00000001

#define    maxn_sp   0x7f7fffff
#define    maxn_msw  0x7fefffff
#define    maxn_lsw  0xffffffff

#define    minn_sp   0x00800000
#define    minn_msw  0x00100000
#define    minn_lsw  0x00000000

#define    min1_sp   0x00800001
#define    min1_msw  0x00100001
#define    min1_lsw  0x00010001

#define    maxd_sp   0x007fffff
#define    maxd_msw  0x000fffff
#define    maxd_lsw  0xffffffff
#define    maxm_sp   0x7eaaaa00
#define    maxm_msw  0x7fd55555
#define    maxm_lsw  0x55554000


#define    nn_sp     0x7f800400
#define    nn_msw    0x7ff00080
#define    nn_lsw    0x00000000
#define    nocare    0

#define    add_sp_l  1
#define    add_dp_l  2
#define    div_sp_l  3
#define    div_dp_l  4
#define    mult_sp_l 5
#define    mult_dp_l 6

struct testws {

     unsigned long   a_msw;
     unsigned long   a_lsw;
     unsigned long   b_msw;
     unsigned long   b_lsw;
     unsigned long   instr;
     unsigned long   status;
};

 
struct testws test_ws[] = {
 /* a_msw    a_lsw    b_msw    b_lsw   instr  status*/
        /* with nxm = 1 */
  {one_sp,   nocare,   maxm_sp,  nocare,   add_sp_l, 0x4 },/* inexact  */
       /*with nxm = 0 or 1 does not care */
  {one_sp,   nocare,   zero_sp,  nocare,   div_sp_l,  0x4},/* div/zero */
  {maxm_sp,  nocare,   maxm_sp,  nocare,   mult_sp_l, 0x4},/* overflow */
  {zero_sp,  nocare,   zero_sp,  nocare,   div_sp_l,  0x4},/* not a valid */
  {maxn_sp,  nocare,   maxn_sp,  nocare,   add_sp_l,  0x4},/* 5-ovfl,inex*/   
  {maxn_sp,  nocare,   maxn_sp,  nocare,   mult_sp_l, 0x4},/* 5-ovfl,inex*/   
  {maxn_msw, maxn_lsw, maxn_msw, maxn_lsw, mult_dp_l, 0x4},
  {one_msw,  one_lsw,  zero_msw, zero_lsw, div_dp_l,  0x4}, 
  {one_sp,   nocare,   nn_sp,    nocare,   add_sp_l,  0x8},
  {one_msw,  one_lsw,  nn_msw,   nn_lsw,   add_dp_l,  0x8},
  {one_sp,   nocare,   nn_sp,    nocare,   mult_sp_l, 0x8},
  {one_msw,  one_lsw,  nn_msw,   nn_lsw,   mult_dp_l, 0x8},
  {maxd_sp,  nocare,   two_sp,   nocare,   div_sp_l,  0x8},/* 8-a-denorm*/ 
  {maxd_msw, maxd_lsw, two_msw,  two_lsw,  div_dp_l,  0x8},
  {min1_sp,  nocare,   pi_4_sp,  nocare,   mult_sp_l, 0x8},/* 7-unfl,inex*/
  {maxd_sp,  nocare,   half_sp,  nocare,   mult_sp_l, 0x8},/* 8 -a-denorm*/
  {maxd_msw, maxd_lsw, half_msw, half_lsw, mult_dp_l, 0x8},
  {half_sp,  nocare,   maxd_sp,  nocare,   mult_sp_l, 0x8},/* 9 -b-denorm*/
  {half_msw, half_lsw, maxd_msw, maxd_lsw, mult_dp_l, 0x8},
  {min1_msw, min1_lsw, pi_4_msw, pi_4_lsw, mult_dp_l, 0x8},
  {nan_sp,   nocare,   zero_sp,  nocare,   add_sp_l,  0x8},/* 12-a-nan*/
  {nan_msw,  nan_lsw,  zero_msw, zero_lsw, add_dp_l,  0x8}, 
  {zero_sp,  nocare,   nan_sp,   nocare,   add_sp_l,  0x8},/* 13 -b-nan*/
  {zero_sp,  nocare,   nan_msw,  nan_lsw,  add_dp_l,  0x8},
  {nan_sp,   nocare,   nan_sp,   nocare,   add_sp_l,  0x8},/* 14 -ab-nan*/
  {nan_msw,  nan_lsw,  nan_msw,  nan_lsw,  add_dp_l,  0x8},
  {nan_sp,   nocare,   zero_sp,  nocare,   mult_sp_l, 0x8},/* 11-a-nan*/
  {nan_msw,  nan_lsw,  zero_msw, zero_lsw, mult_dp_l, 0x8}, 
  {zero_sp,  nocare,   nan_sp,   nocare,   mult_sp_l, 0x8},/* 13-b-nan*/
  {zero_sp,  nocare,   nan_msw,  nan_lsw,  mult_dp_l, 0x8},
  {nan_sp,   nocare,   nan_sp,   nocare,   mult_sp_l, 0x8},/* 14-ab-nan*/
  {nan_msw,  nan_lsw,  nan_msw,  nan_lsw,  mult_dp_l, 0x8},
  {     00,       00,      000,      000,       0000, 0x0}
};


/*
 *	registers.c
 */
unsigned long  pat[] = {
        0x00000000,
        0x55555555,
        0xAAAAAAAA,
        0xCCCCCCCC,
        0xFFFFFFFF
};


/*
 *  	instruction.c
 */	
struct  value {
        unsigned long floatsingle;
        unsigned long floatdouble;
};
struct value rnd[] = {
0x3f000000,   0x3fe00000,
0x3fc00000,   0x3ff80000,
0x40200000,   0x40040000,
0x40600000,   0x400c0000,
0x40900000,   0x40120000,
0x40b00000,   0x40160000,
0x40d00000,   0x401a0000,
0x40f00000,   0x401e0000,
0x41080000,   0x40210000,
0x41180000,   0x40230000,
0x41280000,   0x40250000,
0x41380000,   0x40270000,
0x41480000,   0x40290000,
0x41580000,   0x402a0000,
0x41680000,   0x402c0000,
0x41780000,   0x402f0000
};

struct value val[] = {
0         ,   0,
0x3F800000,   0x3FF00000,
0x40000000,   0x40000000,
0x40400000,   0x40080000,        
0x40800000,   0x40100000,
0x40A00000,   0x40140000,
0x40C00000,   0x40180000,
0x40E00000,   0x401C0000,
0x41000000,   0x40200000,
0x41100000,   0x40220000,
0x41200000,   0x40240000,
0x41300000,   0x40260000,
0x41400000,   0x40280000,
0x41500000,   0x402A0000,
0x41600000,   0x402C0000,
0x41700000,   0x402E0000,
0x41800000,   0x40300000,
0x41880000,   0x40310000,
0x41900000,   0x40320000,
0x41980000,   0x40330000,
0x41a00000,   0x40340000,
0x41a80000,   0x40350000,
0x41b00000,   0x40360000,
0x41b80000,   0x40370000,
0x41c00000,   0x40380000,
0x41c80000,   0x40390000,
0x41d00000,   0x403a0000,
0x41d80000,   0x403b0000,
0x41e00000,   0x403c0000,
0x41e80000,   0x403d0000,
0x41f00000,   0x403e0000,
0x41f80000,   0x403f0000,
0x42000000,   0x40400000,
0x42040000,   0x40408000,
0x42080000,   0x40410000,
0x420c0000,   0x40418000,
0x42100000,   0x40420000,
0x42140000,   0x40428000,
0x42180000,   0x40430000,
0x421c0000,   0x40438000,
0x42200000,   0x40440000,
0x42240000,   0x40448000,
0x42280000,   0x40450000,
0x422c0000,   0x40458000,
0x42300000,   0x40460000,
0x42340000,   0x40468000,
0x42380000,   0x40470000,
0x423c0000,   0x40478000,
0x42400000,   0x40480000,
0x42440000,   0x40488000,
0x42480000,   0x40490000,
0x424c0000,   0x40498000,
0x42500000,   0x404a0000,
0x42540000,   0x404a8000,
0x42580000,   0x404b0000,
0x425c0000,   0x404b8000,
0x42600000,   0x404c0000,
0x42640000,   0x404c8000,
0x42680000,   0x404d0000,
0x426c0000,   0x404d8000,
0x42700000,   0x404e0000,
0x42740000,   0x404e8000,
0x42780000,   0x404f0000,
0x427c0000,   0x404f8000,
0x42800000,   0x40500000,
0x42820000,   0x40504000,
0x42840000,   0x40508000,
0x42860000,   0x4050c000,
0x42880000,   0x40510000,
0x428a0000,   0x40514000,
0x428c0000,   0x40518000,
0x428e0000,   0x4051c000,
0x42900000,   0x40520000,
0x42920000,   0x40524000,
0x42940000,   0x40528000,
0x42960000,   0x4052c000,
0x42980000,   0x40530000,
0x429a0000,   0x40534000,
0x429c0000,   0x40538000,
0x429e0000,   0x4053c000,
0x42a00000,   0x40540000,
0x42a20000,   0x40544000,
0x42a40000,   0x40548000,
0x42a60000,   0x4054c000,
0x42a80000,   0x40550000,
0x42aa0000,   0x40554000,
0x42ac0000,   0x40558000,
0x42ae0000,   0x4055c000,
0x42b00000,   0x40560000,
0x42b20000,   0x40564000,
0x42b40000,   0x40568000,
0x42b60000,   0x4056c000,
0x42b80000,   0x40570000,
0x42ba0000,   0x40574000,
0x42bc0000,   0x40578000,
0x42be0000,   0x4057c000,
0x42c00000,   0x40580000,
0x42c20000,   0x40584000,
0x42c40000,   0x40588000,
0x42c60000,   0x4058c000,
0x42c80000,   0x40590000,
0x42ca0000,   0x40594000,
0x42cc0000,   0x40598000,
0x42ce0000,   0x4059c000,
0x42d00000,   0x405a0000,
0x42d20000,   0x405a4000,
0x42d40000,   0x405a8000,
0x42d60000,   0x405ac000,