📄 fpa_systest.c
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u_long temp_ptr3, temp_ptr4, res1, res2; u_long *ptr1, *ptr2, *ptr3, *ptr4, *ptr5; u_char i, j, k, l, m; /* Initialize by giving the diagnostic initialize command */ *(u_long *) DIAG_INIT_CMD = 0x0; *(u_long *) MODE_WRITE_REGISTER = 0x2; for (i = 0; i < 16; i++) { ptr4 = (u_long *) sp_extd[i].high; ptr5 = (u_long *) sp_extd[i].low; for (j = 0; j < 16; j++) { ptr1 = (u_long *) users[j].reg; *ptr1 = 0x0; ptr1++; *ptr1 = 0x0; } k = (i + 1) & 0xF; ptr2 = (u_long *) users[k].reg; *ptr2 = 0x40000000; /* sp 2 */ *ptr4 = 0x40400000; /* operand1 sp 3 */ *ptr5 = 0x40800000; /* operand2 sp 4 */ for (j = 0; j < 16; j++) { ptr1 = (u_long *) users[j].reg; res1 = *ptr1; if (i == j) { /* it should have the result */ if (res1 != 0x41200000) return (-1); } else if (j == k) { /* reg1 + 1 should have value * sp 2 */ if (res1 != 0x40000000) return (-1); } else if (res1 != 0x0) return (-1); } } return (0);}pointer_dp_ext(){ u_long temp_ptr3, temp_ptr4, res1, res2; u_long *ptr1, *ptr2, *ptr3, *ptr4, *ptr5; u_char i, j, k, l, m; /* Initialize by giving the diagnostic initialize command */ *(u_long *) DIAG_INIT_CMD = 0x0; *(u_long *) MODE_WRITE_REGISTER = 0x2; for (i = 0; i < 16; i++) { ptr4 = (u_long *) dp_extd[i].high; ptr5 = (u_long *) dp_extd[i].low; for (j = 0; j < 16; j++) { ptr1 = (u_long *) users[j].reg; *ptr1 = 0x0; ptr1++; *ptr1 = 0x0; } /* the instru ction is reg[i] = reg[i+2] + (reg[i+1] * operand ) */ k = (i + 1) & 0xF; l = (i + 2) & 0xF; ptr2 = (u_long *) users[k].reg; ptr3 = (u_long *) users[l].reg; *ptr2 = 0x40000000; /* sp 2 , reg[i+1] */ *ptr3 = 0x40080000; /* sp 3 , reg[i+2] */ *ptr4 = 0x40080000; /* operand sp 3 */ *ptr5 = 0x0; for (j = 0; j < 16; j++) { ptr1 = (u_long *) users[j].reg; res1 = *ptr1; if (i == j) { /* it should have the result */ if (res1 != 0x40220000) return (-1); } else if (k == j) { /* reg1 + 1 should have value * sp 2 */ if (res1 != 0x40000000) return (-1); } else if (l == j) { /* reg1 + 2 should have value * sp 3 */ if (res1 != 0x40080000) return (-1); } else if (res1 != 0x0) return (-1); } } return (0);}pointer_short(){ u_long i, j, k, l, m, n, temp_ptr3, temp_ptr4, res1, res2; u_long *ptr1, *ptr2, *ptr3, *ptr4; /* Initialize by giving the diagnostic initialize command */ *(u_long *) DIAG_INIT_CMD = 0x0; *(u_long *) MODE_WRITE_REGISTER = 0x2; for (i = 0; i < 16; i++) { ptr3 = (u_long *) sp_short[i]; for (k = 0; k < 16; k++) { ptr1 = (u_long *) users[k].reg; *ptr1 = 0x0; ptr1++; *ptr1 = 0x0; } ptr1 = (u_long *) users[i].reg; *ptr1 = 0x40000000; /* 2 */ *ptr3 = 0x40C00000; /* sp 6 */ for (k = 0; k < 16; k++) { ptr1 = (u_long *) users[k].reg; res1 = *ptr1; if (i == k) { if (res1 != 0x41000000) return (-1); } else { if (res1 != 0x0) return (-1); } } } for (i = 0; i < 16; i++) { ptr3 = (u_long *) dp_short[i]; ptr4 = (u_long *) 0xE0001000; for (k = 0; k < 16; k++) { ptr1 = (u_long *) users[k].reg; *ptr1 = 0x0; ptr1++; *ptr1 = 0x0; } ptr1 = (u_long *) users[i].reg; *ptr1 = 0x40000000; /* dp 2 */ *ptr3 = 0x40180000; /* dp 6 */ *ptr4 = 0x0; for (k = 0; k < 16; k++) { ptr1 = (u_long *) users[k].reg; res1 = *ptr1; if (i == k) { if (res1 != 0x40200000) return (-1); } else { if (res1 != 0x0) return (-1); } } } return (0);}ptr_incdec_test(){ u_long i, j, k, l, m, n, res1, res2; u_long *ptr, *ptr2, *ptr3; /* Initialize by giving the diagnostic initialize command */ *(u_long *) DIAG_INIT_CMD = 0x0; *(u_long *) MODE_WRITE_REGISTER = 0x2; ptr = (u_long *) 0xE00009B0; /* for transposing */ for (i = 0; i < 1; i++) { for (j = 0; j <= 15; j++) { ptr2 = (u_long *) users[i + j].reg; *ptr2 = j; k = (i + j + 16) & 0x1F; /* so that the register will * be 0 - 31 */ ptr3 = (u_long *) users[k].reg; *ptr3 = 0x100; } *ptr = i; /* now read the transposed values */ j = 0; for (m = 0; m < 4; m++) { for (n = 0; n < 4; n++) { ptr2 = (u_long *) users[i + j].reg; k = (i + j + 16) & 0x1F; /* so that the register will * be 0 - 31 */ ptr3 = (u_long *) users[k].reg; res1 = m + (n * 4); if (*ptr2 != res1) return (-1); if (*ptr3 != 0x100) return (-1); j++; } } } /* Initialize by giving the diagnostic initialize command */ *(u_long *) DIAG_INIT_CMD = 0x0; *(u_long *) MODE_WRITE_REGISTER = 0x2; ptr = (u_long *) 0xE00008CC; /* for dot product */ for (i = 0; i < 32; i++) { ptr2 = (u_long *) users[i].reg; *ptr2 = 0x0; } for (i = 0; i <= 26; i++) { ptr3 = (u_long *) users[i + 5].reg; for (j = 0; j < 32; j++) { ptr2 = (u_long *) users[j].reg; *ptr2 = 0x0; ptr2++; *ptr2 = 0x0; } for (j = 0; j <= 4; j++) { ptr2 = (u_long *) users[i + j].reg; *ptr2 = val[j]; } *ptr = ptr_cmd[i].data; /* send the insrtuction */ res1 = *ptr3; /* get the result */ if (res1 != 0x40440000) return (-1); } return (0);}/* * This routine checks the ram registers for present context */reg_ram(){ u_long *ptr, *ptr1, value1, value2, i, j, pattern, pattern1; ptr = (u_long *) 0xE0000C00; /* starting address for * register ram for present * context */ pattern = 0x1; pattern1 = 0x1; for (j = 0; j < 32; j++) { ptr = (u_long *) 0xE0000C00; for (i = 0; i < 32; i++) { *ptr = pattern; ptr += 1; *ptr = pattern1; ptr += 1; } ptr = (u_long *) 0xE0000C00; for (i = 0; i < 32; i++) { value1 = *ptr; /* for most significant word */ ptr += 1; value2 = *ptr; /* for least significant word */ ptr += 1; if (value1 != pattern) return (-1); if (value2 != pattern1) return (-1); } pattern = (pattern << 1); pattern1 = (pattern1 << 1); } return (0);}/* * The following routine tests the shadow ram for the present context */shadow_ram(){ u_long *ptr, *ptr1, i, j; ptr1 = (u_long *) SHADOW_RAM_START; /* pointer to the start of the * shadow ram */ ptr = (u_long *) 0xE0000C00; /* starting address for * register ram for */ /* present context */ for (i = 0; i < 16; i += 2) { *ptr = i + 1; /* for most significant word */ ptr += 1; *ptr = i; /* for least significant word */ ptr += 1; } for (i = 0; i < 16; i += 2) { if (*ptr1 != (i + 1)) /* higher word of shadow ram */ return (-1); ptr1 += 1; if (*ptr1 != i) /* lower word of shadow ram */ return (-1); ptr1 += 1; } return (0);}wlwf_test(){ u_long *ptr1, *ptr2, *ptr3, *op_ptr, *ptr1_lsw, *ptr2_lsw, *ptr3_lsw; u_long i, res1; /* Initialize by giving the diagnostic initialize command */ *(u_long *) DIAG_INIT_CMD = 0x0; *(u_long *) MODE_WRITE_REGISTER = 0x2; ptr1 = (u_long *) REGISTER_ONE_MSW; ptr1_lsw = (u_long *) REGISTER_ONE_LSW; ptr2 = (u_long *) REGISTER_TWO_MSW; ptr2_lsw = (u_long *) REGISTER_TWO_LSW; ptr3 = (u_long *) REGISTER_THREE_MSW; ptr3_lsw = (u_long *) REGISTER_THREE_LSW; for (i = 0; fval[i].addr != 0x0; i++) { *ptr1 = 0x0; *ptr1_lsw = 0x0; *ptr2 = 0x0; *ptr2_lsw = 0x0; *ptr3 = 0x0; *ptr3_lsw = 0x0; op_ptr = (u_long *) fval[i].addr; *ptr2 = fval[i].reg2; *ptr3 = fval[i].reg3; *op_ptr = 0x30081; /* reg1 <- reg2 op reg3 */ res1 = *ptr1; /* read the result */ if (res1 != fval[i].result) return (-1); } return (0);}check_clear_hardpipe(){ u_long *ierr_ptr, *pipe_status, *hard_pipe; pipe_status = (u_long *) (FPA_BASE + FPA_PIPE_STATUS); hard_pipe = (u_long *) (FPA_BASE + FPA_CLR_PIPEHARD); ierr_ptr = (u_long *) (FPA_BASE + FPA_IERR); if (*ierr_ptr & 0x200000) { printf("warning: pipe is not cleared from prev. oper., clearing now\n"); *hard_pipe = 0x0; }}/* * ================================================ immediate errors register * test subroutine ================================================ */ierr_test(){ register u_long i, j, tmp_data, test_data; u_long *ptr; ptr = (u_long *) FPA_IERR_PTR; for (i = 0; i < 256; i++) { test_data = (i << 16) & 0xFF0000; *ptr = test_data; tmp_data = *ptr & IERR_MASK; if (test_data != tmp_data) return (-1); } return (0);}/* * ================================================ fpa inexact error mask * register test subroutine ================================================ */imask_test(){ u_long *ptr, i, temp_val; ptr = (u_long *) FPA_IMASK_PTR; *ptr = 0; if ((*ptr & 0x1) != 0) return (-1); *ptr = 0x1; if ((*ptr & 0x1) != 0x1) return (-1); return (0);}/* * ================================================ load pointer register * test subroutine ================================================ */ldptr_test(){ register u_long *ram_ptr, i, j, tmp_data, test_data; ram_ptr = (u_long *) FPA_RAM_ACC; test_data = ROTATE_DATA; for (i = 0; i < CNT_ROTATE; i++) { /* you need to mask the unused bits */ test_data &= 0xFFFF; *ram_ptr = test_data; tmp_data = *ram_ptr & 0xFFFF; /* & LPTR_MASK; */ if (test_data != tmp_data) return (-1); test_data = test_data << 1; } return (0);}sim_ins_test(){ u_long index, temp_value; u_long *pipe_status, *addr_ptr; pipe_status = (u_long *) (FPA_BASE + FPA_STABLE_PIPE_STATUS); /* for stabel pipe * status */ for (index = 0; instr1[index].address != 0; index++) { addr_ptr = (u_long *) instr1[index].address; *addr_ptr = 0; temp_value = (*pipe_status & 0xFF0000) >> 16; if (temp_value != instr1[index].status) return (-1); } /* clear the hard pipe */ *(u_long *) FPA_CLEAR_PIPE_PTR = 0x0; return (0);}/* * The following test is for testing the micro store type registers those are * pointer - 5, loop counter, mode register, wstat register * */test_mode_reg(){ int i; u_long *ptr1, *ptr2; /* set the IMASK register = 0 */ *(u_long *) FPA_IMASK_PTR = 0x0; /* clear pipe */ ptr1 = (u_long *) FPA_STATE_PTR; /* *ptr1 = 0x40; */ ptr2 = (u_long *) FPA_CLEAR_PIPE_PTR; *ptr2 = 0x0; ptr1 = (u_long *) (FPA_BASE + FPA_MODE3_0C); ptr2 = (u_long *) (FPA_BASE + FPA_MODE3_0S); for (i = 0; i < 0x10; i++) { /* write into the mode reg. E00008D0 */ *(u_long *) MODE_WRITE_REGISTER = i; /* * now read at two
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