fpa_systest.c

操作系统SunOS 4.1.3版本的源码

	    return (-1);
	}
	temp_test_number = 22;
	if (other_contexts()) {
	    printf("FAILED other contexts\n");
	    fail_close();
	    restore_signals();
	    return (-1);
	}

    open_new_context();
    close_new_context();
}

fail_close()
{
    printf("FPA:                         FAILED!\n");
    close_new_context();		       /* close the context first */
}


/*
 * This routine opens the FPA context, and if it could not checks the error
 * no and prints the error 
 */

open_new_context()
{
    u_long          value;		       /* *st_reg_ptr; */

    st_reg_ptr = (u_long *) FPA_STATE_PTR;
    dev_no = open("/dev/fpa", O_RDWR);

    if (dev_no < 0) {			       /* could not open */

	switch (errno) {

	case ENXIO:
	    printf("FPA: Cannot find FPA.\n");
	    break;
	case ENOENT:
	    printf("FPA: Cannot find 68881.\n");
	    break;
	case EBUSY:
	    printf("FPA: No FPA context Available.\n");
	    break;
	case ENETDOWN:
	    printf("FPA: Disabled FPA, could not access.\n");
	    break;
	case EEXIST:
	    printf("FPA: Duplicate Open on FPA.\n");
	    break;
	}
	return (-1);
    } else
	return (0);
}

close_new_context()
{

    close(dev_no);
}

other_contexts()
{
    int             i, j, value;
    u_long          val, val1;
    /* u_long	*st_reg_ptr; */

    st_reg_ptr = (u_long *) FPA_STATE_PTR;
    for (i = 1; i < 32; i++) {

	if (open_new_context())
	    return (0);
	val = *st_reg_ptr & 0x1F;	       /* get the context number */
	val1 = (1 << val);
	if (verbose  || debug)
	    printf("FPA:    Register Ram Upper Half Test, Context Number = %d\n", val);

	contexts = (contexts | val1);

	if (reg_ram()) {
	    close_new_context();
	    return (-1);
	}
	close_new_context();
    }
    return (0);
}



temp_print()
{
    u_long         *ptr, i;
    u_long         *ptr1;

    ptr1 = (u_long *) (FPA_BASE + FPA_STABLE_PIPE_STATUS);
    ptr = (u_long *) (FPA_BASE + FPA_PIPE_ACT_INS);

    printf("press any key to continue:\n");
    i = getchar();
    printf("        pipe addr = %x,pipe stable3 = %x\n", ptr1, *ptr1);

    for (i = 0; i < 6; i++) {

	printf(" 	addr = %x, value = %x\n", ptr, *ptr);
	ptr++;
    }
}

lock_test()
{

    /* Initialize  by giving the diagnostic initialize command */
    *(u_long *) DIAG_INIT_CMD = 0x0;
    *(u_long *) MODE_WRITE_REGISTER = 0x2;

    *(u_long *) FPA_IMASK_PTR = 0x1;

    if (dp_short_test())
	return (-1);
    if (dp_ext_test())
	return (-1);
    if (dp_cmd_test())
	return (-1);
    if (next_dp_short_test())
	return (-1);
    if (next_dp_ext_test())
	return (-1);
    if (next_dp_cmd_test())
	return (-1);

    return (0);
}

next_dp_short_test()
{
    u_long          res_a_msw, res_a_lsw, res_n_msw, res_n_lsw, res_i_msw, res_i_lsw;
    int             i, j, k;
    u_long          res0_msw, res0_lsw, shad_res_msw, shad_res_lsw, value_i, value_0;
    u_long         *soft_clear, *reg0, *reg0_lsw, *reg0_addr, *reg0_addr_lsw;
    u_long         *reg_i, *reg_i_lsw, *reg_i_addr, *reg_i_addr_lsw, *shadow_j, *shadow_j_lsw;
    u_long         *ptr4_lsw, *ptr4, *ptr5_lsw, *ptr5;
    u_long          res4_msw, res5_msw, res4_lsw, res5_lsw;
    u_long         *ptr2, *ptr2_lsw;

    soft_clear = (u_long *) FPA_CLEAR_PIPE_PTR;
    for (i = 0; i < 16; i++) {
	ptr2 = (u_long *) user[i].reg_msw;
	ptr2_lsw = (u_long *) user[i].reg_lsw;

	/* initialize */
	*ptr2 = 0x0;
	*ptr2_lsw = 0x0;
    }
    res_a_msw = 0x3FD55555;		       /* the result is always active
					        * - dp value 0.33333333333 */
    res_a_lsw = 0x55555555;
    res_n_msw = 0x3FE55555;		       /* the result of next should
					        * be always be 0.6666666666 */
    res_n_lsw = 0x55555555;
    value_0 = 0x3FF00000;
    value_i = 0x40000000;
    reg0 = (u_long *) REGISTER_ZERO_MSW;       /* always this register will
					        * be active */
    reg0_lsw = (u_long *) REGISTER_ZERO_LSW;

    reg0_addr = (u_long *) dps[0].addr;	       /* for higher significant
					        * value */
    reg0_addr_lsw = (u_long *) 0xE0001000;     /* for least significant value */

    for (i = 0; i < 16; i++) {

	reg_i_addr = (u_long *) dps[i].addr;   /* for higher significant
					        * value */
	reg_i_addr_lsw = (u_long *) 0xE0001000;/* for least significant value */
	reg_i = (u_long *) user[i].reg_msw;
	reg_i_lsw = (u_long *) user[i].reg_lsw;
	for (j = 0; j < 8; j++) {

	    shadow_j = (u_long *) shadow[j].shreg_msw;
	    shadow_j_lsw = (u_long *) shadow[j].shreg_lsw;
	    *reg0 = 0x3FF00000;		       /* register 0 has dp value of
					        * 1 - active stage */
	    *reg0_lsw = 0x0;
	    *reg_i = 0x40000000;	       /* register has dp value of 2
					        * for next stage2 for next
					        * stage */
	    *reg_i_lsw = 0x0;

	    *(u_long *) FPA_IMASK_PTR = 0x1;

	    *reg0_addr = 0x40080000;	       /* operand has dp value of 3
					        * active stage */
	    *reg0_addr_lsw = 0x0;
	    *reg_i_addr = 0x40080000;	       /* operand  has dp value 3
					        * next stage */
	    *reg_i_addr_lsw = 0x0;

	    /* may be soft clear */
	    shad_res_msw = *shadow_j;	       /* read the shadow register */
	    shad_res_lsw = *shadow_j_lsw;
	    *soft_clear = 0x0;

	    res_i_msw = *reg_i;		       /* read the result from the
					        * reg  i */
	    res_i_lsw = *reg_i_lsw;
	    res0_msw = *reg0;
	    res0_lsw = *reg0_lsw;

	    *(u_long *) FPA_IMASK_PTR = 0x0;

	    if ((j == 0) && (j == i)) {
		if ((shad_res_msw != 0x3FCC71C7) || (res_i_msw != 0x3FCC71C7) || (res0_msw != 0x3FCC71C7))
		    /*
		     * if ((shad_res_msw != res_n_msw) || (res_i_msw !=
		     * res_n_msw) || (res0_msw != res_n_msw)) 
		     */
		{

		    printf("Err1:reg = %x, shadow = %x, rres= %x, sres = %x\n",
			   i, j, res0_msw, shad_res_msw);
		    printf("res0_lsw = %x, shad_lsw = %x, resi_msw = %x, resi_lsw = %x\n",
			   res0_lsw, shad_res_lsw, res_i_msw, res_i_lsw);
		    return (-1);
		}
	    } else if ((j == 0) && (j != i)) {
		if ((shad_res_msw != res_a_msw) || (res_i_msw != res_n_msw) || (res0_msw != res_a_msw)) {

		    printf("Err2:reg = %x, shadow = %x, rres= %x, sres = %x\n",
			   i, j, res0_msw, shad_res_msw);
		    printf("res_i_msw = %x\n", res_i_msw);
		    return (-1);
		}
	    } else if ((j != 0) && (j == i)) {

		if ((shad_res_msw != res_n_msw) || (res_i_msw != res_n_msw) || (res0_msw != res_a_msw)) {
		    printf("Err3:reg = %x, shadow = %x, rres= %x, sres = %x\n",
			   i, j, res0_msw, shad_res_msw);
		    printf("res_i_msw = %x\n", res_i_msw);
		    return (-1);
		}
	    } else if ((j != 0) && (j != i)) {
		if (i == 0) {
		    if ((shad_res_msw != 0x0) || (res_i_msw != value_i) || (res0_msw != value_i)) {
			printf("Err4:reg = %x, shadow = %x, rres= %x, sres = %x\n",
			       i, j, res0_msw, shad_res_msw);
			printf("res_i_msw = %x\n", res_i_msw);
			return (-1);
		    }
		} else if ((shad_res_msw != 0x0) || (res_i_msw != value_i) || (res0_msw != value_0)) {
		    printf("Err4:reg = %x, shadow = %x, rres= %x, sres = %x\n",
			   i, j, res0_msw, shad_res_msw);
		    printf("res_i_msw = %x\n", res_i_msw);
		    return (-1);
		}
	    }
	    *reg0 = 0x0;
	    *reg0_lsw = 0x0;
	    *reg_i = 0x0;
	    *reg_i_lsw = 0x0;
	}
	*ptr2 = 0x0;
	*ptr2_lsw = 0x0;
    }
    return (0);

}
next_dp_ext_test()
{
    u_long          res_a_msw, res_a_lsw, res_n_msw, res_n_lsw, res_i_msw, res_i_lsw;
    int             i, j, k;
    u_long          res0_msw, res0_lsw, shad_res_msw, shad_res_lsw, value_i, value_0;
    u_long         *soft_clear, *reg0, *reg0_lsw, *reg0_addr, *reg0_addr_lsw;
    u_long         *reg_i, *reg_i_lsw, *reg_i_addr, *reg_i_addr_lsw, *shadow_j, *shadow_j_lsw;
    u_long         *ptr4_lsw, *ptr4, *ptr5_lsw, *ptr5;
    u_long          res4_msw, res5_msw, res4_lsw, res5_lsw;
    u_long         *ptr2, *ptr2_lsw;

    soft_clear = (u_long *) FPA_CLEAR_PIPE_PTR;
    for (i = 0; i < 16; i++) {
	ptr2 = (u_long *) user[i].reg_msw;
	ptr2_lsw = (u_long *) user[i].reg_lsw;

	/* initialize */
	*ptr2 = 0x0;
	*ptr2_lsw = 0x0;
    }
    res_a_msw = 0x3FD55555;		       /* the result is always active
					        * - dp value 0.33333333333 */
    res_a_lsw = 0x55555555;
    res_n_msw = 0x3FE55555;		       /* the result of next should
					        * be always be 0.6666666666 */
    res_n_lsw = 0x55555555;
    value_0 = 0x3FF00000;
    value_i = 0x40000000;
    reg0 = (u_long *) REGISTER_ZERO_MSW;       /* always this register will
					        * be active */
    reg0_lsw = (u_long *) REGISTER_ZERO_LSW;

    reg0_addr = (u_long *) ext[0].addr;	       /* for higher significant
					        * value */
    reg0_addr_lsw = (u_long *) ext[0].addr_lsw;/* for least significant value */
    for (i = 0; i < 16; i++) {

	reg_i_addr = (u_long *) ext[i].addr;   /* for higher significant
					        * value */
	reg_i_addr_lsw = (u_long *) ext[i].addr_lsw;	/* for least significant
							 * value */
	reg_i = (u_long *) user[i].reg_msw;
	reg_i_lsw = (u_long *) user[i].reg_lsw;
	for (j = 0; j < 8; j++) {

	    shadow_j = (u_long *) shadow[j].shreg_msw;
	    shadow_j_lsw = (u_long *) shadow[j].shreg_lsw;
	    *reg0 = 0x3FF00000;		       /* register 0 has dp value of
					        * 1 - active stage */
	    *reg0_lsw = 0x0;
	    *reg_i = 0x40000000;	       /* register has dp value of 2
					        * for next stage2 for next
					        * stage */
	    *reg_i_lsw = 0x0;
	    *(u_long *) FPA_IMASK_PTR = 0x1;

	    *reg0_addr = 0x40080000;	       /* operand has dp value of 3
					        * active stage */
	    *reg0_addr_lsw = 0x0;
	    *reg_i_addr = 0x40080000;	       /* operand  has dp value 3
					        * next stage */
	    *reg_i_addr_lsw = 0x0;
	    /* may be soft clear */
	    shad_res_msw = *shadow_j;	       /* read the shadow register */
	    shad_res_lsw = *shadow_j_lsw;
	    *soft_clear = 0x0;
	    res_i_msw = *reg_i;		       /* read the result from the
					        * reg  i */
	    res_i_lsw = *reg_i_lsw;
	    res0_msw = *reg0;
	    res0_lsw = *reg0_lsw;
	    *(u_long *) FPA_IMASK_PTR = 0x0;

	    if ((j == 0) && (j == i)) {
		if ((shad_res_msw != 0x3FCC71C7) || (res_i_msw != 0x3FCC71C7) || (res0_msw != 0x3FCC71C7))
		    /*
		     * if ((shad_res_msw != res_n_msw) || (res_i_msw !=
		     * res_n_msw) || (res0_msw != res_n_msw)) 
		     */
		{

		    printf("Err1:reg = %x, shadow = %x, rres= %x, sres = %x\n",
			   i, j, res0_msw, shad_res_msw);
		    printf("res0_lsw = %x, shad_lsw = %x, resi_msw = %x, resi_lsw = %x\n",
			   res0_lsw, shad_res_lsw, res_i_msw, res_i_lsw);
		    return (-1);
		}
	    } else if ((j == 0) && (j != i)) {
		if ((shad_res_msw != res_a_msw) || (res_i_msw != res_n_msw) || (res0_msw != res_a_msw)) {

		    printf("Err2:reg = %x, shadow = %x, rres= %x, sres = %x\n",
			   i, j, res0_msw, shad_res_msw);
		    printf("res_i_msw = %x\n", res_i_msw);
		    return (-1);
		}
	    } else if ((j != 0) && (j == i)) {

		if ((shad_res_msw != res_n_msw) || (res_i_msw != res_n_msw) || (res0_msw != res_a_msw)) {
		    printf("Err3:reg = %x, shadow = %x, rres= %x, sres = %x\n",
			   i, j, res0_msw, shad_res_msw);
		    printf("res_i_msw = %x\n", res_i_msw);
		    return (-1);
		}
	    } else if ((j != 0) && (j != i)) {
		if (i == 0) {
		    if ((shad_res_msw != 0x0) || (res_i_msw != value_i) || (res0_msw != value_i)) {
			printf("Err4:reg = %x, shadow = %x, rres= %x, sres = %x\n",
			       i, j, res0_msw, shad_res_msw);
			printf("res_i_msw = %x\n", res_i_msw);
			return (-1);
		    }
		} else if ((shad_res_msw != 0x0) || (res_i_msw != value_i) || (res0_msw != value_0)) {
		    printf("Err4:reg = %x, shadow = %x, rres= %x, sres = %x\n",
			   i, j, res0_msw, shad_res_msw);
		    printf("res_i_msw = %x\n", res_i_msw);
		    return (-1);
		}
	    }
	    *reg0 = 0x0;
	    *reg0_lsw = 0x0;
	    *reg_i = 0x0;
	    *reg_i_lsw = 0x0;
	}
	*ptr2 = 0x0;
	*ptr2_lsw = 0x0;
    }
    return (0);

}
next_dp_cmd_test()
{
    u_long          res_a_msw, res_a_lsw, res_n_msw, res_n_lsw, res_i_msw, res_i_lsw;
    int             i, j, k;
    u_long          res0_msw, res0_lsw, shad_res_msw, shad_res_lsw, value_i, value_0;
    u_long         *soft_clear, *reg0, *reg0_lsw, *reg0_addr, *reg0_addr_lsw;
    u_long         *reg_i, *reg_i_lsw, *reg_i_addr, *reg_i_addr_lsw, *shadow_j, *shadow_j_lsw;
    u_long         *ptr4_lsw, *ptr4, *ptr5_lsw, *ptr5;
    u_long          res4_msw, res5_msw, res4_lsw, res5_lsw;
    u_long         *ptr2, *ptr2_lsw;

    soft_clear = (u_long *) FPA_CLEAR_PIPE_PTR;
    for (i = 0; i < 32; i++) {
	ptr2 = (u_long *) user[i].reg_msw;
	ptr2_lsw = (u_long *) user[i].reg_lsw;

	/* initialize */
	*ptr2 = 0x0;
	*ptr2_lsw = 0x0;
    }
    res_a_msw = 0x1;			       /* the result is always active
					        * - 0.333333333333 */
    res_a_lsw = 0x0;
    res_n_msw = 0x2;			       /* the result of next should
					        * be always be 0.6666666666 */
    res_n_lsw = 0x0;
    value_0 = 0x1;
    value_i = 0x2;
    reg0 = (u_long *) REGISTER_ZERO_MSW;       /* always this register will
					        * be active */
    reg0_lsw = (u_long *) REGISTER_ZERO_LSW;

    reg0_addr = (u_long *) 0xE0000AC4;
    reg_i_addr = (u_long *) 0xE0000AC4;
    for (i = 0; i < 31; i++) {

	reg_i = (u_long *) user[i].reg_msw;
	reg_i_lsw = (u_long *) user[i].reg_lsw;
	for (j = 0; j < 8; j++) {

	    shadow_j = (u_long *) shadow[j].shreg_msw;
	    shadow_j_lsw = (u_long *) shadow[j].shreg_lsw;
	    *reg0 = value_0;		       /* register 0 has dp value of
					        * 0.333 - active stage */
	    *reg0_lsw = 0x0;
	    *reg_i = value_i;		       /* register has dp value of
					        * 0.666for next stage2 for
					        * next stage */
	    *reg_i_lsw = 0x0;
	    *(u_long *) FPA_IMASK_PTR = 0x1;

	    *reg0_addr = nxt_cmd[0].data;      /* nota number + 0 weitek op */

	    *reg_i_addr = nxt_cmd[i].data;     /* nota number + 0 weitek op */

	    /* may be soft clear */
	    shad_res_msw = *shadow_j;	       /* read the shadow register */
	    shad_res_lsw = *shadow_j_lsw;

	    *soft_clear = 0x0;

	    res_i_msw = *reg_i;		       /* read the result from the
					        * reg  i */
	    res_i_lsw = *reg_i_lsw;

	    res0_msw = *reg0;
	    res0_lsw = *reg0_lsw;
	    *(u_long *) FPA_IMASK_PTR = 0x0;

	    if ((j == 0) && (j == i)) {
		if ((shad_res_msw != value_i) || (res_i_msw != value_i) || (res0_msw != value_i))
		    /*
		     * if ((shad_res_msw != res_n_msw) || (res_i_msw !=
		     * res_n_msw) || (res0_msw != res_n_msw)) 
		     */
		{

		    printf("Err1:reg = %x, shadow = %x, rres= %x, sres = %x\n",
			   i, j, res0_msw, shad_res_msw);
		    printf("res0_lsw = %x, shad_lsw = %x, resi_msw = %x, resi_lsw = %x\n",
			   res0_lsw, shad_res_lsw, res_i_msw, res_i_lsw);
		    return (-1);
		}
	    } else if ((j == 0) && (j != i)) {
		if ((shad_res_msw != res_a_msw) || (res_i_msw != res_n_msw) || (res0_msw != res_a_msw)) {

		    printf("Err2:reg = %x, shadow = %x, rres= %x, sres = %x\n",
			   i, j, res0_msw, shad_res_msw);
		    printf("res_i_msw = %x\n", res_i_msw);
		    return (-1);
		}
	    } else if ((j != 0) && (j == i)) {

		if ((shad_res_msw != res_n_msw) || (res_i_msw != res_n_msw) || (res0_msw != res_a_msw)) {
		    printf("Err3:reg = %x, shadow = %x, rres= %x, sres = %x\n",
			   i, j, res0_msw, shad_res_msw);
		    printf("res_i_msw = %x\n", res_i_msw);
		    return (-1);
		}
	    } else if ((j != 0) && (j != i)) {
		if (i == 0) {
		    if ((shad_res_msw != 0x0) || (res_i_msw != value_i) || (res0_msw != value_i)) {
			printf("Err4:reg = %x, shadow = %x, rres= %x, sres = %x\n",
			       i, j, res0_msw, shad_res_msw);
			printf("res_i_msw = %x\n", res_i_msw);
			return (-1);
		    }