fpa3x_dev.c

操作系统SunOS 4.1.3版本的源码

/******************************************************************************
	@(#)fpa3x_dev.c - Rev 1.1 - 7/30/92
	Copyright (c) 1988 by Sun Microsystems, Inc.
	Deyoung Hong

	FPA-3X device specific test functions.
******************************************************************************/

#include <stdio.h>
#include <errno.h>
#include <varargs.h>
#include <sys/types.h>
#include <sundev/fpareg.h>
#include "../../include/sdrtns.h"	/* make sure not from local directory */
#include "fpa3x_def.h"
#include "fpa3x_msg.h"


/* External declarations */
extern struct fpa_device *fpa;
extern int fpa_version;
extern int fd;

 
/* WSTATUS expected value read corresponding to value written 0 thru F */
static u_int wstatexp[] =
{
	WSTAT0, WSTAT1, WSTAT2, WSTAT3, WSTAT4, WSTAT5, WSTAT6, WSTAT7,
	WSTAT8, WSTAT9, WSTATA, WSTATB, WSTATC, WSTATD, WSTATE, WSTATF, 0
};


/* Simple instruction and status test */
static struct
{
	int inst;		/* instruction sequence */
	int stat;		/* expected pipe status */
} simple[] =
{
	{ SP_NOP,		FPA_PIPE_CLEAR				    },
	{ DP_NOP,		FPA_PIPE_CLEAR | FPA_WAIT2 | FPA_IDLE2 |
							    FPA_FIRST_V_ACT },
	{ DP_LSW,		FPA_PIPE_CLEAR				    },
	{ INS_UNIMPLEMENT,	FPA_PIPE_CLEAR | FPA_HUNG | FPA_FIRST_V_ACT },
	{ 0,			0					    }
};


/* Jump condition data test table */
static struct
{
	u_int inst;		/* command instruction */
	u_int data;		/* reg2 data value */
	u_int result;		/* reg1 result expected */
} jumpcond[] =
{
	{ CSP_SINE,	SZERO,	SZERO		},
	{ CSP_SINE,	SVAL1,	SINE_SVAL1	},
	{ CSP_SINE,	SVAL2,	SINE_SVAL2	},
	{ CSP_SINE,	SONE,	SINE_SONE	},
	{ CSP_SINE,	SMONE,	SINE_SMONE	},
	{ CSP_ARCTAN,	STWO,	ATAN_STWO	},
	{ CSP_ARCTAN,	SVAL3,	ATAN_SVAL3	},
	{ CSP_ARCTAN,	SVAL4,	ATAN_SVAL4	},
	{ 0,		0,	0		}
};


/* Single precision short instruction operation test table */
static struct
{
	u_int inst;		/* instruction */
	u_int reg1;		/* reg1 value */
	u_int op;		/* operand value */
	u_int result;		/* reg1 result expected */
} spshort[] =
{
	{ SP_NEGATE,	X,		SONE,		SMONE		},
	{ SP_ABS,	X,		SMONE,		SONE		},
	{ SP_FLOAT,	X,		4,		SFOUR		},
	{ SP_FIX,	X,		SSIXTEEN,	16		},
	{ SP_TODOUBLE,	X,		SNINE,		DNINE_M		},
	{ SP_SQUARE,	X,		SFOUR,		SSIXTEEN	},
	{ SP_ADD,	STHREE,		SSIX,		SNINE		},
	{ SP_SUB,	SNINE,		SONE,		SEIGHT		},
	{ SP_MULT,	STWO,		SFIVE,		STEN		},
	{ SP_DIVIDE,	SEIGHT,		SFOUR,		STWO		},
	{ SP_RSUB,	STHREE,		SFOUR,		SONE		},
	{ SP_RDIVIDE,	SONE,		SEIGHT,		SEIGHT		},
	{ 0,		0,		0,		0		}
};


/* Double precision short instruction operation test table */
static struct
{
	u_int inst;		/* instruction */
	u_int reg1;		/* reg1 value */
	u_int op;		/* operand most significant value */
	u_int result;		/* reg1 result expected */
} dpshort[] =
{
	{ DP_NEGATE,	X,		DONE_M,		DMONE_M		},
	{ DP_ABS,	X,		DMONE_M,	DONE_M		},
	{ DP_FLOAT,	X,		4,		DFOUR_M		},
	{ DP_FIX,	X,		DSIXTEEN_M,	16		},
	{ DP_TOSINGLE,	X,		DNINE_M,	SNINE		},
	{ DP_SQUARE,	X,		DFOUR_M,	DSIXTEEN_M	},
	{ DP_ADD,	DTHREE_M,	DSIX_M,		DNINE_M		},
	{ DP_SUB,	DNINE_M,	DONE_M,		DEIGHT_M	},
	{ DP_MULT,	DTWO_M,		DFIVE_M,	DTEN_M		},
	{ DP_DIVIDE,	DEIGHT_M,	DFOUR_M,	DTWO_M		},
	{ DP_RSUB,	DTHREE_M,	DFOUR_M,	DONE_M		},
	{ DP_RDIVIDE,	DONE_M,		DEIGHT_M,	DEIGHT_M	},
	{ 0,		0,		0,		0		}
};


/* Single precision extended instruction operation test table */
static struct
{
	u_int inst;		/* instruction */
	u_int reg2;		/* reg2 value */
	u_int op;		/* operand value */
	u_int reg1;		/* reg1 result value */
} spext[] =
{
	{ XSP_ADD,	STHREE,		SSIX,		SNINE		},
	{ XSP_SUB,	SNINE,		SONE,		SEIGHT		},
	{ XSP_MULT,	STWO,		SFIVE,		STEN		},
	{ XSP_DIVIDE,	SEIGHT,		SFOUR,		STWO		},
	{ XSP_RSUB,	STHREE,		SFOUR,		SONE		},
	{ XSP_RDIVIDE,	SONE,		SEIGHT,		SEIGHT		},
	{ 0,		0,		0,		0		}
};


/* Single precision extended two operations test table */ 
static struct
{
	u_int inst;		/* instruction */
	u_int op2;		/* second operand value */
	u_int reg2;		/* reg2 value */
	u_int op1;		/* first operand value */
	u_int reg1;		/* reg1 result value */
} spext2[] =
{
	{ XSP_R1_O2aR2xO,	STWO,	SONE,	STHREE,	SFIVE		},
	{ XSP_R1_O2sR2xO,	STEN,	STWO,	STHREE,	SFOUR		},
	{ XSP_R1_mO2aR2xO,	SONE,	STWO,	STWO,	STHREE		},
	{ XSP_R1_O2xR2aO,	SONE,	STHREE,	SSIX,	SNINE		},
	{ XSP_R1_O2xR2sO,	SONE,	STWO,	STHREE,	SMONE		},
	{ XSP_R1_O2xmR2aO,	SFOUR,	STWO,	SSIX,	SSIXTEEN	},
	{ 0,			0,	0,	0,	0		}
};


/* Double precision extended instruction operation test table */
static struct
{
	u_int inst;		/* instruction */
	u_int reg2;		/* reg2 value */
	u_int op;		/* operand value */
	u_int reg1;		/* reg1 result value */
} dpext[] =
{
	{ XDP_ADD,	DTHREE_M,	DSIX_M,		DNINE_M		},
	{ XDP_SUB,	DNINE_M,	DONE_M,		DEIGHT_M	},
	{ XDP_MULT,	DTWO_M,		DFIVE_M,	DTEN_M		},
	{ XDP_DIVIDE,	DEIGHT_M,	DFOUR_M,	DTWO_M		},
	{ XDP_RSUB,	DTHREE_M,	DFOUR_M,	DONE_M		},
	{ XDP_RDIVIDE,	DONE_M,		DEIGHT_M,	DEIGHT_M	},
	{ 0,		0,		0,		0		}
};


/* Single precision command register operation test */
static struct
{
	u_int inst;		/* instruction */
	u_int reg3;		/* reg3 value */
	u_int reg2;		/* reg2 value */
	u_int reg4;		/* reg4 value */
	u_int reg1;		/* reg1 result value */
} spcmd[] =
{
	{ CSP_R1_R2,		X,	STEN,	X,	STEN		},
	{ CSP_R1_R3aR2xR4,	STHREE,	STWO,	STHREE,	SNINE		},
	{ CSP_R1_R3sR2xR4,	STEN,	SONE,	STWO,	SEIGHT		},
	{ CSP_R1_mR3aR2xR4,	SSIX,	STWO,	STHREE,	SZERO		},
	{ CSP_R1_R3xR2aR4,	SFOUR,	STWO,	STWO,	SSIXTEEN	},
	{ CSP_R1_R3xR2sR4,	SNINE,	SFOUR,	STHREE,	SNINE		},
	{ CSP_R1_R3xmR2aR4,	STEN,	STWO,	STHREE,	STEN		},
	{ 0,			0,	0,	0,	0		}
};


/* Double precision command register operation test */
static struct
{
	u_int inst;		/* instruction */
	u_int reg3;		/* reg3 most significant value */
	u_int reg2;		/* reg2 most significant value */
	u_int reg4;		/* reg4 most significant value */
	u_int reg1;		/* reg1 most significant result value */
} dpcmd[] =
{
	{ CDP_R1_R2,		X,	   DTEN_M,    X,	DTEN_M     },
	{ CDP_R1_R3aR2xR4,	DTHREE_M,  DTWO_M,    DTHREE_M, DNINE_M    },
	{ CDP_R1_R3sR2xR4,	DTEN_M,	   DONE_M,    DTWO_M,   DEIGHT_M   },
	{ CDP_R1_mR3aR2xR4,	DSIX_M,	   DTWO_M,    DTHREE_M, DZERO_M    },
	{ CDP_R1_R3xR2aR4,	DFOUR_M,   DTWO_M,    DTWO_M,   DSIXTEEN_M },
	{ CDP_R1_R3xR2sR4,	DNINE_M,   DFOUR_M,   DTHREE_M, DNINE_M    },
	{ CDP_R1_R3xmR2aR4,	DTEN_M,	   DTWO_M,    DTHREE_M, DTEN_M     },
	{ 0,			0,	   0,	      0,	0	   }
};


/* TI status test table structure */
struct tistat_tbl
{
	u_int inst;		/* operation */
	u_int reg2_ms, reg2_ls;	/* reg2 */
	u_int reg3_ms, reg3_ls;	/* reg3 */
	u_int stat;		/* TI expected status */
};


/* TI status test table with ALU functions */
static struct tistat_tbl alu[] =
{
	{ CWSP_ADD,    SZERO,     X,         SZERO,     X,         TI_ZERO   },
	{ CWDP_ADD,    DZERO_M,   DZERO_L,   DZERO_M,   DZERO_L,   TI_ZERO   },
	{ CWSP_ADD,    SINF,      X,         SINF,      X,         TI_INFIN  },
	{ CWDP_ADD,    DINF_M,    DINF_L,    DINF_M,    DINF_L,    TI_INFIN  },
	{ CWSP_ADD,    SONE,      X,         SONE,      X,         TI_FINEX  },
	{ CWDP_ADD,    DONE_M,    DONE_L,    DONE_M,    DONE_L,    TI_FINEX  },
	{ CWSP_DIVIDE, SONE,      X,         SPI,       X,         TI_FININ  },
	{ CWDP_DIVIDE, DONE_M,    DONE_L,    DPI_M,     DPI_L,     TI_FININ  },
	{ CWSP_ADD,    SMAXNORM,  X,         SMAXNORM,  X,         TI_OVFIN  },
	{ CWDP_ADD,    DMAXNORM_M,DMAXNORM_L,DMAXNORM_M,DMAXNORM_L,TI_OVFIN  },
	{ CWSP_DIVIDE, SMINNORM,  X,         STWO,      X,         TI_UNDFEX },
	{ CWDP_DIVIDE, DMINNORM_M,DMINNORM_L,DTWO_M,    DTWO_L,    TI_UNDFEX },
	{ CWSP_DIVIDE, SMINNORM,  X,         SPI,       X,         TI_UNDFIN },
	{ CWDP_DIVIDE, DMINNORM_M,DMINNORM_L,DPI_M,     DPI_L,     TI_UNDFIN },
	{ CWSP_DIVIDE, SMAXSUB,   X,         STWO,      X,         TI_ADNORM },
	{ CWDP_DIVIDE, DMAXSUB_M, DMAXSUB_L, DTWO_M,    DTWO_L,    TI_ADNORM },
	{ CWSP_DIVIDE, STWO,      X,         SMAXSUB,   X,         TI_BDNORM },
	{ CWDP_DIVIDE, DTWO_M,    DTWO_L,    DMAXSUB_M, DMAXSUB_L, TI_BDNORM },
	{ CWSP_DIVIDE, SMAXSUB,   X,         SMAXSUB,   X,         TI_ABDNORM},
	{ CWDP_DIVIDE, DMAXSUB_M, DMAXSUB_L, DMAXSUB_M, DMAXSUB_L, TI_ABDNORM},
	{ CWSP_DIVIDE, SONE,      X,         SZERO,     X,         TI_DIVZERO},
	{ CWDP_DIVIDE, DONE_M,    DONE_L,    DZERO_M,   DZERO_L,   TI_DIVZERO},
	{ CWSP_ADD,    SSNAN,     X,         SZERO,     X,         TI_ANAN   },
	{ CWDP_ADD,    DSNAN_M,   DSNAN_L,   DZERO_M,   DZERO_L,   TI_ANAN   },
	{ CWSP_ADD,    SZERO,     X,         SSNAN,     X,         TI_BNAN   },
	{ CWDP_ADD,    DZERO_M,   DZERO_L,   DSNAN_M,   DSNAN_L,   TI_BNAN   },
	{ CWSP_ADD,    SSNAN,     X,         SSNAN,     X,         TI_ABNAN  },
	{ CWDP_ADD,    DSNAN_M,   DSNAN_L,   DSNAN_M,   DSNAN_L,   TI_ABNAN  },
	{ CWSP_DIVIDE, SINF,      X,         SINF,      X,         TI_INVAL  },
	{ CWDP_DIVIDE, DINF_M,    DINF_L,    DINF_M,    DINF_L,    TI_INVAL  },
	{ 0,           0,         0,         0,         0,         0         }
};


/* TI status test table with multiplier functions */
static struct tistat_tbl mul[] =
{
	{ CWSP_MULT,   SZERO,     X,         SZERO,     X,         TI_ZERO   },
	{ CWDP_MULT,   DZERO_M,   DZERO_L,   DZERO_M,   DZERO_L,   TI_ZERO   },
	{ CWSP_MULT,   SINF,      X,         SINF,      X,         TI_INFIN  },
	{ CWDP_MULT,   DINF_M,    DINF_L,    DINF_M,    DINF_L,    TI_INFIN  },
	{ CWSP_MULT,   SONE,      X,         SONE,      X,         TI_FINEX  },
	{ CWDP_MULT,   DONE_M,    DONE_L,    DONE_M,    DONE_L,    TI_FINEX  },
	{ CWSP_MULT,   SPI,       X,         SPI,       X,         TI_FININ  },
	{ CWDP_MULT,   DPI_M,     DPI_L,     DPI_M,     DPI_L,     TI_FININ  },
	{ CWSP_MULT,   SMAXNORM,  X,         SMAXNORM,  X,         TI_OVFIN  },
	{ CWDP_MULT,   DMAXNORM_M,DMAXNORM_L,DMAXNORM_M,DMAXNORM_L,TI_OVFIN  },
	{ CWSP_MULT,   SMINNORM,  X,         SHALF,     X,         TI_UNDFEX },
	{ CWDP_MULT,   DMINNORM_M,DMINNORM_L,DHALF_M,   DHALF_L,   TI_UNDFEX },
	{ CWSP_MULT,   SMIN1,     X,         SPIO4,     X,         TI_UNDFIN },
	{ CWDP_MULT,   DMIN1_M,   DMIN1_L,   DPIO4_M,   DPIO4_L,   TI_UNDFIN },
	{ CWSP_MULT,   SMINSUB,   X,         SHALF,     X,         TI_ADNORM },
	{ CWDP_MULT,   DMINSUB_M, DMINSUB_L, DHALF_M,   DHALF_L,   TI_ADNORM },
	{ CWSP_MULT,   SHALF,     X,         SMINSUB,   X,         TI_BDNORM },
	{ CWDP_MULT,   DHALF_M,   DHALF_L,   DMINSUB_M, DMINSUB_L, TI_BDNORM },
	{ CWSP_MULT,   SMINSUB,   X,         SMINSUB,   X,         TI_ABDNORM},
	{ CWDP_MULT,   DMINSUB_M, DMINSUB_L, DMINSUB_M, DMINSUB_L, TI_ABDNORM},
	{ CWSP_MULT,   SSNAN,     X,         SZERO,     X,         TI_ANAN   },
	{ CWDP_MULT,   DSNAN_M,   DSNAN_L,   DZERO_M,   DZERO_L,   TI_ANAN   },
	{ CWSP_MULT,   SZERO,     X,         SSNAN,     X,         TI_BNAN   },
	{ CWDP_MULT,   DZERO_M,   DZERO_L,   DSNAN_M,   DSNAN_L,   TI_BNAN   },
	{ CWSP_MULT,   SSNAN,     X,         SSNAN,     X,         TI_ABNAN  },
	{ CWDP_MULT,   DSNAN_M,   DSNAN_L,   DSNAN_M,   DSNAN_L,   TI_ABNAN  },
	{ CWSP_MULT,   SINF,      X,         SZERO,     X,         TI_INVAL  },
	{ CWDP_MULT,   DINF_M,    DINF_L,    DZERO_M,   DZERO_L,   TI_INVAL  },
	{ 0,           0,         0,         0,         0,         0         }
};


/* TI timing test table with single precision short instructions */
static struct
{
	u_int inst;		/* instruction */
	u_int reg1;		/* reg1 value */
	u_int op;		/* operand value */
	u_int result;		/* reg1 result expected */
} timsp[] =
{
	{ SP_SQUARE,	X,		SONE,		SONE		},
	{ SP_SQUARE,	X,		STWO,		SFOUR		},
	{ SP_SQUARE,	X,		STHREE,		SNINE		},
	{ SP_SQUARE,	X,		SFOUR,		SSIXTEEN	},
	{ SP_DIVIDE,	SSIX,		STHREE,		STWO		},
	{ SP_DIVIDE,	SSIX,		STWO,		STHREE		},
	{ SP_DIVIDE,	SEIGHT,		SFOUR,		STWO		},
	{ SP_DIVIDE,	SSIXTEEN,	SFOUR,		SFOUR		},
	{ 0,		0,		0,		0		}
};


/* TI timing test table with double precision short instructions */
static struct
{
	u_int inst;		/* instruction */
	u_int reg1;		/* reg1 value */
	u_int op;		/* operand value */
	u_int result;		/* reg1 result expected */
} timdp[] =
{
	{ DP_SQUARE,	X,		DONE_M,		DONE_M		},
	{ DP_SQUARE,	X,		DTWO_M,		DFOUR_M		},
	{ DP_SQUARE,	X,		DTHREE_M,	DNINE_M		},
	{ DP_SQUARE,	X,		DFOUR_M,	DSIXTEEN_M	},
	{ DP_DIVIDE,	DSIX_M,		DTHREE_M,	DTWO_M		},
	{ DP_DIVIDE,	DSIX_M,		DTWO_M,		DTHREE_M	},
	{ DP_DIVIDE,	DEIGHT_M,	DFOUR_M,	DTWO_M		},
	{ DP_DIVIDE,	DSIXTEEN_M,	DFOUR_M,	DFOUR_M		},
	{ 0,		0,		0,		0		}
};


/* TI timing test table with extended dp instructions */
static struct
{
	u_int inst;		/* instruction */
	u_int op;		/* data operand */
	u_int reg3;		/* data assigned to reg3 */
	u_int reg2;		/* data assigned to reg2 */
	u_int reg1;		/* expected result in reg1 */
} timext[] =
{
	{ XDP_R1_R3aR2xO,  DTWO_M,     DTWO_M,     DFOUR_M,  DTEN_M },
	{ XDP_R1_R3sR2xO,  DTWO_M,     DSIXTEEN_M, DTHREE_M, DTEN_M },
	{ XDP_R1_mR3aR2xO, DTWO_M,     DTWO_M,     DSIX_M,   DTEN_M },
	{ XDP_R1_R3xR2aO,  DTWO_M,     DTWO_M,     DTHREE_M, DTEN_M },
	{ XDP_R1_R3xR2sO,  DTWO_M,     DFIVE_M,    DFOUR_M,  DTEN_M },
	{ XDP_R1_R3xmR2aO, DSEVEN_M,   DTWO_M,	   DTWO_M,   DTEN_M },
	{ XDP_R1_OaR3xR2,  DFOUR_M,    DTHREE_M,   DTWO_M,   DTEN_M },
	{ XDP_R1_OsR3xR2,  DSIXTEEN_M, DTHREE_M,   DTWO_M,   DTEN_M },
	{ XDP_R1_mOaR3xR2, DTWO_M,     DSIX_M,     DTWO_M,   DTEN_M },
	{ XDP_R1_OxR3aR2,  DTWO_M,     DFOUR_M,    DONE_M,   DTEN_M },
	{ XDP_R1_OxR3sR2,  DTWO_M,     DSIX_M,     DONE_M,   DTEN_M },
	{ 0,               0,          0,          0,        0      }
};


/* TI timing test table with command register dp instructions */
static struct
{
	u_int inst;		/* instruction */
	u_int ms2, ls2;		/* data assigned to reg2 */
	u_int ms1, ls1;		/* expected result in reg1 */
} timcmd[] =
{
	{ CDP_R1_eR2s1,	DTHIRTY2_M, DTHIRTY2_L, DEXP32S1_M, DEXP32S1_L },
	{ CDP_R1_eR2s1, DSIXTEEN_M, DSIXTEEN_L, DEXP16S1_M, DEXP16S1_L },
	{ CDP_R1_eR2s1, DEIGHT_M,   DEIGHT_L,   DEXP8S1_M,  DEXP8S1_L  },
	{ CDP_R1_eR2s1, DFOUR_M,    DFOUR_L,    DEXP4S1_M,  DEXP4S1_L  },
	{ 0,            0,          0,          0,          0          }
};


/*
 * This function tests the IERR register by write/read all patterns
 * in bits 23-16 of the register.
 */
ierr_test()
{
	register u_int w, k;
	u_int r;

	send_message(0,VERBOSE,tst_reg,"IERR");

	for (k = 0; k <= BYTE_MAX; k++)
	{
		w = k << IERR_SHIFT;
		if (write_fpa(&fpa->fp_ierr,w,ON)) return;
		if (read_fpa(&fpa->fp_ierr,&r,ON)) return;
		r &= IERR_MASK;
		if (w != r) send_message(FPERR,ERROR,er_reg,"IERR",w,r);
	}
}


/*
 * This function tests the IMASK register by write all patterns in bits 3-0
 * of register, then verifies bits 3-1 are always 001 and bit 0 is compared.
 */
imask_test()
{
	register u_int w;
	u_int r;

	send_message(0,VERBOSE,tst_reg,"IMASK");

	for (w = 0; w <= NIBBLE_MAX; w++)
	{
		if (write_fpa(&fpa->fp_imask,w,ON)) return;
		if (read_fpa(&fpa->fp_imask,&r,ON)) return;
		r &= IMASK_MASK;
		if ((w & FPA_INEXACT | fpa_version) != r)
			send_message(FPERR,ERROR,er_reg,"IMASK",w,r);
	}
}


/*
 * This function tests the LOAD_PTR register by write/read all hex patterns 
 * from 0 to FFFF.
 */
loadptr_test()
{
	register u_int w;
	u_int r;

	send_message(0,VERBOSE,tst_reg,"LOAD_PTR");

	for (w = 0; w <= WORD_MAX; w++)
	{
		if (write_fpa(&fpa->fp_load_ptr,w,ON)) return;
		if (read_fpa(&fpa->fp_load_ptr,&r,ON)) return;
		r &= LOADPTR_MASK;
		if (w != r) send_message(FPERR,ERROR,er_reg,"LOAD_PTR",w,r);
	}
}