svr4fpu-test.s

操作系统SunOS 4.1.3版本的源码

/* static char  frefsccsid[] = "@(#)svr4fpu-test.s 1.1 7/30/92 Copyright Sun Microsystems"; */
!****************************************************************************
! 
!
!****************************************************************************
! Function:	This is the test module for Sundiag.  All of the test and
!		assembler level diagnostic code is here.  All of the inter-
!		face code is in the fpu-if.s module.
!****************************************************************************

        .seg    ".text"

	.global	datap_add
	.global datap_mult
	.global datap_add_dp
	.global datap_mult_dp
	.global timing_add_sp
	.global timing_mult_sp
	.global timing_add_dp
	.global timing_mult_dp
	.common result_msw,4,4
	.common result_lsw,4,4
	.global clear_regs
	.global register_test
	.global move_regs
	.global branches
	.global trap_remove
	.global fpu_exc	
	.global int_float_e

	.seg    ".data"
        .align  8
temp:		.skip 4
temp1:		.skip 4
temp2:		.skip 4
wdp: 		.skip 4		! storage location for a single precision
wdp1:  		.skip 4		! storage location for a double precision
wdp2:   	.skip 4		! storage for extended

dp_result: 	.skip 4
result_msw: 	.skip 4
result_lsw: 	.skip 4
 
 
	.seg	".text"

!++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
! Name:		
! Function:	This routine test the data path of weitek adder for single 
!		precision.
! Calling:	i0 = value
! Returns:	
! Convention:	
!--------------------------------------------------------------------------
!
!		f0 = value
!		f1 = 0
!	add =   f2 = value
!
datap_add:
	save    %sp, -88, %sp	! save the stack frame
	set	wdp, %l0	! get a memory address
	set	wdp1, %l1	! .. one for the result
	set	0x0, %l3	! .. get a zero
	st	%l3, [%l1]	! .... and store it in memory
	st	%i0, [%l0]	! .... store the value passed 
	ld	[%l0], %f0	! .... put the passed value into f0
	ld	[%l1], %f1	! .... put value 0 into reg f1
	fadds   %f0, %f1, %f2   ! ...... add zero and value into f2
	fcmps	%f0, %f2	! .... check the value passed and added value 
	nop			! .... delay
	fbe	datap_ok	! .. if they are equal
	nop			! .... delay
datap_no:
	st	%f2, [%l1]	! return the result on error
datap_ok:
	ld	[%l1], %i0	! then return a zero
	ret			! .... delay
	restore


!++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
! Name:		
! Function:	
! Calling:	
! Returns:	
! Convention:	
!--------------------------------------------------------------------------
! 
! This routine test the data path of weitek multiplier for single precision
!              f0 = value
!              f1 = 1 
!      mult =  f2 = f0 * f1
!
datap_mult:
	save    %sp, -88, %sp
        set     wdp, %l0
        set     wdp1, %l1
        set     0x3F800000, %l3		!put value 1 into memoruy
	st      %l3, [%l1] 
        st      %i0, [%l0]      !store the value passed into memory location
        ld      [%l0], %f0      ! put the passed value into f0 
        ld      [%l1], %f1      ! put value 1 into reg f1 
        fmuls   %f0, %f1, %f2	! multiply value with 1 , it has to be same
	fcmps   %f0, %f2
	nop
	fbne	datap_no
	nop
	set	0x0, %l3
	st	%l3, [%l1]
	ba	datap_ok
	nop


!++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
! Name:		
! Function:	
! Calling:	
! Returns:	
! Convention:	
!--------------------------------------------------------------------------
!
!	This routine tests the data path of the weitek multiplier for 
!	double precision 
!
!              f0 = msw value
!		f1 = lsw value
!		f2 = 0
!		f3 = 0
!	add =   f4 = f0 + f2
!
datap_add_dp:
	save    %sp, -88, %sp  
        set     wdp, %l0       
        set     wdp1, %l1  
	set	wdp2, %l2
	set	result_msw, %l4
	set	result_lsw,%l5
	set	0x0, %l3	!put value 0 into memoruy      
        st      %l3, [%l1]
	st	%i0, [%l0]	! msw of value
        st	%i1, [%l2]	! lsw of value
	ld	[%l0], %f0	! put the msw into f0
	ld	[%l2], %f1	! put the lsw into f1
	ld	[%l1], %f2	! put 0 into f2
	ld	[%l1], %f3	! put 0 into f3
	faddd   %f0, %f2, %f4	! add value + 0 into f4
	fcmpd   %f0, %f4	! now compare the result
	nop
	fbe	datap_ok	! good
	nop
!*	stfd	%f4, [%l4]
	st	%f4, [%l4]
	st	%f5, [%l5]
	nop
	set	0x1, %l3
	st	%l3, [%l1]
	ba	datap_ok	! no good but code is already set		
	nop

!++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
! Name:		
! Function:	
! Calling:	
! Returns:	
! Convention:	
!--------------------------------------------------------------------------
!
!  This routine tests the data path of the weitek multiplier for 
!  double precision      
!
!              f0 = msw value 
!              f1 = lsw value 
!              f2 = 0
!              f3 = 0
!	mult = f4 = f0 * f2
!
datap_mult_dp:
	save    %sp, -88, %sp  
        set     wdp, %l0       
        set     wdp1, %l1      
        set     wdp2, %l2      
        set     result_msw, %l4
	set	result_lsw, %l5
        set     0x3FF00000, %l3 ! put value 1  into memoruy      
        st      %l3, [%l1]     
        st      %i0, [%l0]      ! msw of value 
        st      %i1, [%l2]      ! lsw of value 
        ld      [%l0], %f0      ! put the msw into f0  
        ld      [%l2], %f1      ! put the lsw into f1  
        ld      [%l1], %f2      ! put 1 into f2
	set	0x0, %l3
	st	%l3, [%l1]
        ld      [%l1], %f3	! put 0 into f3, i.e f2 = 0x3ff00000 dp of 1 
	fmuld	%f0, %f2, %f4   ! mult value * 1 into f4
	fcmpd   %f0, %f4	! now compare the result
	nop 
        fbe     datap_ok        ! good
	nop 
!*        stfd    %f4, [%l4]       
	st	%f4, [%l4]
	st	%f5, [%l5]
        nop
        set     0x1, %l3         
        st      %l3, [%l1]     
        ba      datap_ok        ! no good but code is already set 
	nop
!
! for add routine all the f registers from 0 - 19 will be filled with numbers
! and the result should be 10.
!
timing_add_sp:
	save    %sp, -88, %sp	! save the registers, stacck
        set     wdp, %l0
	set	wdp1, %l1
	set	wdp2, %l2
	set	0x0, %l3
	set     0x3f800000, %l4 ! put value 1 
	set	0x41200000, %l5	! put value 10 into local 5
	st	%l5, [%l0]
	st	%l4, [%l1]
	st	%l3, [%l2]
	ld	[%l0], %f31	! register 31 has 10
	ld	[%l1], %f30	! register 30 has 1

	ld	[%l2], %f0	! reg 0 has 0
	fmovs   %f31, %f1	! reg1 has 10
	fsubs   %f31, %f30, %f18! reg 18 has 9
	fmovs   %f18, %f3	! reg 3 has 9
	fmovs   %f30, %f2	! reg 2 has 1
	fmovs   %f30, %f19	! reg 19 has 1
	fsubs   %f18, %f19, %f16! reg 16 has 8
	fmovs   %f16, %f5	! reg 5 has 8
	fsubs   %f31, %f16, %f17! reg 17 has 2
	fmovs	%f17, %f4	! reg 4 has 2
	fsubs   %f16, %f30, %f14! reg 14 has 7 
	fmovs   %f14, %f7	! reg 7 has 7
	fsubs   %f31, %f14, %f15! reg 15 has 3
	fmovs	%f15, %f6	! reg 6 has 3
	fsubs   %f14, %f30, %f12! reg 12 has 6
	fmovs	%f12, %f9	! reg 9 has 6
	fsubs   %f31, %f12, %f13! reg 13 has 4
	fmovs	%f13, %f8	! reg 8 has 4
	fsubs   %f12, %f30, %f10! reg 10 has 5
	fmovs	%f10, %f11	! reg 11 has 5

	fadds	%f0, %f1, %f20		! reg 0 + reg 1 = reg 20 = 10
	fadds   %f2, %f3, %f21		! reg 2 + reg 3 = reg 21 = 10
	fadds   %f4, %f5, %f22		! reg 4 + reg 5 = reg 22 = 10
	fadds   %f6, %f7, %f23		! reg 6 + reg 7 = reg 23 = 10
	fadds   %f8, %f9, %f24		! reg 8 + reg 9 = reg 24 = 10
	fadds   %f10, %f11, %f25	! reg 10 + reg 11 = reg 25 = 10
	fadds   %f12, %f13, %f26	! reg 12 + reg 13 = reg 26 = 10
	fadds   %f14, %f15, %f27	! reg 14 + reg 15 = reg 27 = 10
	fadds   %f16, %f17, %f28	! reg 16 + reg 17 = reg 28 = 10
	fadds   %f18, %f19, %f29	! reg 18 + reg 19 = reg 29 = 10
!
treg20:					!  Now additions are done check it out
	fcmps	%f31, %f20
	nop
	fbe	treg21			! go to check next one
	nop
r20:
	st	%f20, [%l2]
	ba	done
	nop
treg21:
	fcmps	%f31, %f21
	nop
	fbe	treg22
	nop
r21:
	st	%f21, [%l2]      
        ba      done
        nop
treg22:	
	fcmps   %f31, %f22
	nop
	fbe	treg23
	nop
r22:
	st	%f22, [%l2]            
        ba      done   
        nop    
treg23:
	fcmps	%f31, %f23
	nop
	fbe     treg24 
        nop 
r23:
        st      %f23, [%l2]             
        ba      done    
        nop        
treg24:   
        fcmps   %f31, %f24 
	nop
        fbe     treg25  
        nop  
r24:
        st      %f24, [%l2]              
        ba      done     
        nop         
treg25:    
        fcmps   %f31, %f25  
	nop
        fbe     treg26   
        nop   
r25:
        st      %f25, [%l2]               
        ba      done      
        nop          
treg26:     
        fcmps   %f31, %f26   
	nop
        fbe     treg27    
        nop    
r26:
        st      %f26, [%l2]                
        ba      done       
        nop           
treg27:      
        fcmps   %f31, %f27    
	nop
        fbe     treg28     
        nop     
r27:
        st      %f27, [%l2]                 
        ba      done        
        nop            
treg28:       
        fcmps   %f31, %f28     
	nop
        fbe     treg29      
        nop      
r28:
        st      %f28, [%l2]                  
        ba      done         
        nop             
treg29:        
        fcmps   %f31, %f28      
	nop
        fbe     reggood
	nop
r29:
	st	%f29, [%l2]
	nop
done:
reggood:
	ld	[%l2], %i0
	ret
        restore
!
!	for mult routine all the f registers from 0 - 19 will be filled 
!	with numbers and the result should be the number.
!
timing_mult_sp:
	save    %sp, -88, %sp           ! save the registers, stacck
        set     wdp, %l0
        set     wdp1, %l1
        set     wdp2, %l2
        set     0x0, %l3
	set	0x3f800000, %l4         ! put value 1 
        set     0x41200000, %l5         ! put value 10 into local 5
        st      %l5, [%l0]
        st      %l4, [%l1]
        st      %l3, [%l2]
        ld      [%l0], %f31             ! register 31 has 10
        ld      [%l1], %f1              ! register 1 has 1
	fmovs   %f1, %f3
	fmovs   %f1, %f5
	fmovs   %f1, %f7
	fmovs   %f1, %f9
	fmovs   %f1, %f11		! register 1, 3, 5, 7, 9, 11, 13, 15, 17, 19
	fmovs   %f1, %f13		! has a value of 1
	fmovs   %f1, %f15
	fmovs   %f1, %f17
	fmovs   %f1, %f19		!
	fmovs	%f1, %f0
	fmovs   %f31, %f18		! reg 18 has 10
	fsubs	%f31, %f0, %f16		! reg 16  has 9
	fsubs   %f16, %f0, %f14		! reg 14 has 8
	fsubs   %f14, %f0, %f12		! reg 12 has 7
	fsubs   %f12, %f0, %f10		! reg 10 has 6
	fsubs   %f10, %f0, %f8		! reg 8 has 5
	fsubs   %f8, %f0, %f6		! reg 6 has 4
	fsubs   %f6, %f0, %f4		! reg 4 has 3
	fsubs   %f4, %f0, %f2		! reg 2 has 2

	fmuls   %f0, %f1, %f20          ! reg 0 * reg 1 = reg 20 = 1
        fmuls   %f2, %f3, %f21          ! reg 2 * reg 3 = reg 21 = 2 
        fmuls   %f4, %f5, %f22          ! reg 4 * reg 5 = reg 22 = 3 
        fmuls   %f6, %f7, %f23          ! reg 6 * reg 7 = reg 23 = 4 
        fmuls   %f8, %f9, %f24          ! reg 8 * reg 9 = reg 24 = 5 
        fmuls   %f10, %f11, %f25        ! reg 10 * reg 11 = reg 25 = 6 
        fmuls   %f12, %f13, %f26        ! reg 12 * reg 13 = reg 26 = 7 
        fmuls   %f14, %f15, %f27        ! reg 14 * reg 15 = reg 27 = 8  
        fmuls   %f16, %f17, %f28        ! reg 16 * reg 17 = reg 28 = 9 
        fmuls   %f18, %f19, %f29        ! reg 18 * reg 19 = reg 29 = 10

	fcmps	%f0, %f20
	nop
	fbe	m21
	nop
	ba	r20
	nop
m21:
	fcmps	%f2, %f21
	nop
	fbe	m22
	nop
	ba	r21
	nop
m22:
	fcmps   %f4, %f22
	nop
	fbe 	m23
	nop
	ba	r22
	nop
m23:
	fcmps	%f6, %f23
	nop
	fbe	m24
	nop
	ba	r23
	nop
m24:
	fcmps	%f8, %f24
	nop
	fbe	m25
	nop
	ba	r24
	nop
m25:
	fcmps	%f10, %f25
	nop
	fbe	m26
	nop
	ba	r25
	nop
m26:
	fcmps	%f12, %f26
	nop
	fbe	m27
	nop
	ba	r26
	nop
m27:
	fcmps	%f14, %f27
	nop
	fbe	m28
	nop
	ba	r27
	nop
m28:
	fcmps	%f16, %f28
	nop
	fbe	m29
	nop
	ba	r28
	nop
m29:
	fcmps	%f18, %f29
	nop
	fbe	reggood
	nop	
	ba	r29
	nop
!
!	same thing for double precision
!
timing_add_dp:
	save    %sp, -88, %sp           ! save the registers, stacck
        set     wdp, %l0
        set     wdp1, %l1
        set     wdp2, %l2
        set     0x0, %l3
	set	0x3ff00000, %l4         ! put value 1 
        set     0x40240000, %l5         ! put value 10 into local 5
        st      %l5, [%l0]
        st      %l4, [%l1]
        st      %l3, [%l2]
	ld	[%l0], %f30             ! register 30 has 10
	fmovs   %f30, %f2		! reg 2 has 10
	ld	[%l2], %f0		! reg 0 has 0
	ld	[%l1], %f4		! reg 4 has 1
	fsubd	%f30, %f4, %f6		! reg 6 has 9
	fsubd	%f6, %f4, %f10		! reg 10 has 8
	fsubd   %f30, %f10, %f8		! reg 8 has 2
	fsubd	%f10, %f4, %f14		! reg 14 has 7
	fsubd   %f30, %f14, %f12	! reg 12 has 3
	fsubd	%f14, %f4, %f18		! reg 18 has 6
	fsubd	%f30, %f18, %f16	! reg 16 has 4
!
	faddd	%f0, %f2, %f20		! reg 20 has 10
	faddd   %f4, %f6, %f22		! reg 22 has 10
	faddd   %f8, %f10, %f24		! reg 24 has 10
	faddd   %f12, %f14, %f26	! reg 26 has 10
	faddd   %f16, %f18, %f28	! reg 28 has 10
!
	fcmpd	%f30, %f20
	nop
	fbe	d22
	nop
	st	%f20, [%l2]
	ba	nogood
	nop
d22:
	fcmpd	%f30, %f22
	nop
	fbe	d24
	nop
	st	%f22, [%l2]      
        ba      nogood
        nop
d24:
	fcmpd   %f30, %f24     
	nop	
        fbe     d26
	nop
        st      %f24, [%l2]            
        ba      nogood 
        nop    
d26:
        fcmpd   %f30, %f26     
	nop
        fbe     d28    
	nop
        st      %f26, [%l2]            
        ba      nogood 
        nop    
d28:
	fcmpd	%f30, %f28
	nop
	fbe	good	
	nop
	st	%f28, [%l2]