smreg.h

操作系统SunOS 4.1.3版本的源码

/*
 * @(#)smreg.h 1.1 92/07/30 Copyright (c) 1988 by Sun Microsystems, Inc.
 *
 *	Emulex ESP SCSI (low-level) driver header file
 *
 *	11/88	KSAM	Add in supports for Billie installation
 *	5/88	KSAM	Add in supports for Hydra, Campus, and P4-ESP
 *	2/88	KSAM	initial written for Stingray
 *
 */
#if (defined sun3x) || (defined sun4)

/* must be byte accesses in Campus */
/*
 * Emules ESP (Enhanced SCSM Controller) Registers.
 */
/* read of ESP's registers yields the following: */
struct esp_read_reg {	/* for P4 card, it is always 32 bit access */
	u_char	xcnt_lo;	/* transfer counter (low byte)*/
	u_char	pad1;
	u_char	pad2;
	u_char	pad3;
	u_char	xcnt_hi;	/* transfer counter (high byte)*/
	u_char	pad5;
	u_char	pad6;
	u_char	pad7;
	u_char	fifo_data;	/* fifo data buffer */
	u_char	pad9;
	u_char	pad10;
	u_char	pad11;
	u_char	cmd;		/* command register */
	u_char	pad12;
	u_char	pad13;
	u_char	pad14;
	u_char	stat;		/* status register */
	u_char	pad16;
	u_char	pad17;
	u_char	pad18;
	u_char	intr;		/* interrupt status register */
	u_char	pad19;
	u_char	pad20;
	u_char	pad21;
	u_char	step;		/* sequence step register */
	u_char	pad22;
	u_char	pad23;
	u_char	pad24;
	u_char	fifo_flag;	/* fifo flag register */
	u_char	pad25;
	u_char	pad26;
	u_char	pad27;
	u_char	conf;		/* configuration register, */
	u_char	pad28;
	u_char	pad29;
	u_char	pad30;
	u_char	reserved1;	/* reservered */
	u_char	pad31;
	u_char	pad32;
	u_char	pad33;
	u_char	reserved2;	/* reservered */
	u_char	pad34;
	u_char	pad35;
	u_char	pad36;
	u_char	conf2;		/* ESP-II configuration register */
};

/* write of ESP's registers yields the following: */
struct esp_write_reg {	/* for P4 card, it is always 32 bit access */
	u_char	xcnt_lo;	/* transfer counter (low byte)*/
	u_char	pad1;
	u_char	pad2;
	u_char	pad3;
	u_char	xcnt_hi;	/* transfer counter (high byte)*/
	u_char	pad5;
	u_char	pad6;
	u_char	pad7;
	u_char	fifo_data;	/* fifo data buffer */
	u_char	pad9;
	u_char	pad10;
	u_char	pad11;
	u_char	cmd;		/* command register */
	u_char	pad13;
	u_char	pad14;
	u_char	pad15;
	u_char	busid;		/* bus_id register */
	u_char	pad16;
	u_char	pad17;
	u_char	pad18;
	u_char	timeout;	/* timeout limit register */
	u_char	pad19;
	u_char	pad20;
	u_char	pad21;
	u_char	sync_period;	/* sync period register */
	u_char	pad22;
	u_char	pad23;
	u_char	pad24;
	u_char	sync_offset;	/* sync offset register */
	u_char	pad25;
	u_char	pad26;
	u_char	pad27;
	u_char	conf;		/* configuration register, */
	u_char	pad28;
	u_char	pad29;
	u_char	pad30;
	u_char	clock_conv;	/* clock convertion register */
	u_char	pad31;
	u_char	pad32;
	u_char	pad33;
	u_char	test;		/* test register */
	u_char	pad34;
	u_char	pad35;
	u_char	pad36;
	u_char	conf2;		/* ESP-II configuration register */
	u_char	pad38;
	u_char	pad39;
	u_char	pad40;
};

/* DMA GATE-ARRAY registers */
struct udc_table {
	u_long	ctl_stat;	/* 32 bit for HYDRA */
	u_long	dma_addr;	/* 32 bit dor hydra */
};

#define STINGRAY 		1		/* boot ID_PROM type */
#define HYDRA 			2
#define CAMPUS 			3

#define STINGRAY_BUSID 		0		/* bit 31-28 in DVMA status reg */
#define CAMPUS_BUSID		1
#define HYDRA_BUSID		2
#define SM_SIZE			0x2000		/* ESP and DVMA space */	

#define P4DVMA_SCSI_BASE	0xff600000
#define STINGRAY_SCSI_BASE	0xfa000000
#define STINGRAY_DMA_OFFSET	0x1000		/* SCSI_BASE + OFFSET */

#define CAMPUS_SCSI_BASE	0xf8800000
#define CAMPUS_DMA_OFFSET	0x400000	/* SCSI_BASE - OFFSET */

#define HYDRA_SCSI_BASE		0x66000000
#define HYDRA_DMA_OFFSET	0x1000		/* SCSI_BASE + OFFSET */

#define P4ESP_SCSI_BASE		0xff200200
#define P4ESP_DMA_OFFSET	0x103		/* SCSI_BASE + OFFSET */

/* bits in the ESP's initiator command register */
#define CMD_DMA		0x80	/* =1= enable DMA */

/* Several common Initiator cammand */
#define	CMD_NOP		0x0	/* misc cammand */	/* NO INT */
#define	CMD_FLUSH	0x1				/* NO INT */
#define	CMD_RESET_ESP	0x2				/* NO INT */
#define	CMD_RESET_SCSI	0x3				/* NO INT */
#define	CMD_RESEL_SEQ	0x40	/* disconnect cammand */	
#define	CMD_SEL_NOATN	0x41
#define	CMD_SEL_ATN	0x42
#define	CMD_SEL_STOP 	0x43
#define	CMD_EN_RESEL	0x44				/* NO INT */
#define	CMD_DIS_RESEL	0x45
#define	CMD_TRAN_INFO	0x10	/* initiator cmd */
#define	CMD_COMP_SEQ	0x11
#define	CMD_MSG_ACPT	0x12
#define	CMD_TRAN_PAD	0x18
#define	CMD_SET_ATN	0x1a				/* NO INT */


/* bits in the ESP's status register (read only) 	*/
#define ESP_STAT_RES	0x80	/* reserved */
#define ESP_STAT_GERR	0x40	/* gross error */
#define ESP_STAT_PERR	0x20	/* parity error */
#define ESP_STAT_XZERO	0x10	/* transfer counter zero */
#define ESP_STAT_XCMP	0x8	/* transfer completed */
#define ESP_STAT_MSG	0x4	/* scsi phase bit: MSG */
#define ESP_STAT_CD	0x2	/* scsi phase bit: CD */
#define ESP_STAT_IO	0x1	/* scsi phase bit: IO */
#define STAT_ERR_MASK	(ESP_STAT_GERR | ESP_STAT_PERR)

/* settings of status to reflect different information transfer phases */
#define ESP_PHASE_MASK		(ESP_STAT_MSG | ESP_STAT_CD | ESP_STAT_IO)
#define ESP_PHASE_DATA		(ESP_PHASE_DATA_IN | ESP_PHASE_DATA_OUT)
#define ESP_PHASE_DATA_OUT	0
#define ESP_PHASE_DATA_IN	(ESP_STAT_IO)
#define ESP_PHASE_COMMAND	(ESP_STAT_CD)
#define ESP_PHASE_STATUS	(ESP_STAT_CD | ESP_STAT_IO)
#define ESP_PHASE_MSG_OUT	(ESP_STAT_MSG | ESP_STAT_CD)
#define ESP_PHASE_MSG_IN	(ESP_STAT_MSG | ESP_STAT_CD | ESP_STAT_IO)

#define ESP_PHASE_SMURIOUS	0x80	/* for driver use only */
#define ESP_PHASE_ARBITRATION	0x81	/* for driver use only */
#define ESP_PHASE_IDENTIFY	0x82	/* for driver use only */
#define ESP_PHASE_SAVE_PTR	0x83	/* for driver use only */
#define ESP_PHASE_RESTORE_PTR	0x84	/* for driver use only */
#define ESP_PHASE_DISCONNECT	0x85	/* for driver use only */
#define ESP_PHASE_CMD_CPLT	0x86	/* for driver use only */


/* bits in the ESP's interrupt status register */
#define ESP_INT_RESET	0x80	/* SCSI reset detected */
#define ESP_INT_ILLCMD	0x40	/* illegal cmd */
#define ESP_INT_DISCON	0x20	/* disconnect */
#define ESP_INT_BUS	0x10	/* bus service */
#define ESP_INT_FCMP	0x8	/* function completed */
#define ESP_INT_RESEL	0x4	/* reselected */
#define ESP_INT_SELATN	0x2	/* selected with ATN */
#define ESP_INT_SEL	0x1	/* selected without ATN */
#define ESP_INT_MASK	0xfc	/* all execpt least 2 bits */

#define INT_OK_MASK	(ESP_INT_BUS | ESP_INT_FCMP)
#define INT_RESEL_OK	(ESP_INT_RESEL | ESP_INT_FCMP)
#define INT_RESEL_OK1	(ESP_INT_RESEL | ESP_INT_BUS)
#define INT_DISCON_OK	(ESP_INT_DISCON | ESP_INT_FCMP)
#define INT_DISCON_OK1	(ESP_INT_DISCON | ESP_INT_BUS)
#define INT_ILL_BUS		(ESP_INT_ILLCMD | ESP_INT_BUS)
#define INT_ILL_FCMP		(ESP_INT_ILLCMD | ESP_INT_FCMP)
#define INT_ILL_DISCON		(ESP_INT_ILLCMD | ESP_INT_DISCON)
#define INT_ILL_DISCON_OK	(ESP_INT_ILLCMD | INT_DISCON_OK)
#define INT_ILL_DISCON_OK1	(ESP_INT_ILLCMD | INT_DISCON_OK1)
#define INT_ILL_RESEL		(ESP_INT_ILLCMD | ESP_INT_RESEL)
#define INT_ILL_RESEL_OK	(ESP_INT_ILLCMD | INT_RESEL_OK)
#define INT_ILL_RESEL_OK1	(ESP_INT_ILLCMD | INT_RESEL_OK1)

/* bits in the ESP's step sequnce register */
#define ESP_SEQ_STEP		0x7	/* last 3 bits */

/* bits in the ESP's configuration register */
#define ESP_CONF_SLOWMODE	0x80	/* slow cable mode */
#define ESP_CONF_DISRINT	0x40	/* disable reset int */
#define ESP_CONF_PARTEST	0x20	/* parity test mode */
#define ESP_CONF_PAREN		0x10	/* enable parity */
#define ESP_CONF_CHIPTEST	0x8	/* chip test mode */
#define ESP_CONF_BUSID		0x7	/* last 3 bits to be host id 7 */
#define DEF_ESP_HOSTID		0x7	/* higher priority */

/* bits in the DVMA status register */
#define DVMA_INTPEND	0x1	/* (r) interrupt pending, clear when ESP stops INT */
#define DVMA_ERRPEND	0x2	/* (r) error pendinf on meory exception */
#define DVMA_PACKCNT	0xc	/* (r) number of bytes in reg_pack */
#define DVMA_INTEN	0x10	/* (r/w) interrupt enable */
#define DVMA_FLUSH	0x20	/* (w) =1= clears PACKCNT and ERRPEND */
#define DVMA_DRAIN	0x40	/* (r/w) =1= pushes PACKCNT bytes to memory */