libm.il

操作系统SunOS 4.1.3版本的源码

!	.asciz	"@(#)libm.il 1.1 92/07/30 SMI"

!	Copyright (c) 1989 by Sun Microsystems, Inc.
!	@(#)RELEASE libm.il, 4.1 alpha 9 

! x0 = 0x44	! shadow area of %o0
! x1 = 0x48	! shadow area of %o1
! x2 = 0x4c	! shadow area of %o2
! x3 = 0x50	! shadow area of %o3
! x4 = 0x54	! shadow area of %o4
! x5 = 0x58	! shadow area of %o5
! 
! List of inline expansion libm functions
! __swapEX, __swapRD, __swapRP, __swapTE
! _fp_class, _ir_fp_class, _copysign, _r_copysign_
! _finite,  _ir_finite_
! _signbit, _ir_signbit
! _isinf, _isnan, _isnormal, _issubnormal, _iszero
! _abs, _fabs, _r_fabs_
!! _irint, _ir_irint_
!
! _Facos, _Faint, _Fanint, _Fasin, _Fatan, _Fcos, _Fcosh, _Fexp, _Fexp10
! _Fexp2, _Flog, _Flog10, _Fnint, _Fsin, _Fsinh, _Ftan, _Ftanh
!
! ___infinity	 (request by POSIX)
! 
! List of inline expansion libF77 functions
! _i_nint, _i_dnnt 
!
! __Fc_minus, __Fc_add, __Fc_neg,
! __Ff_conv_c, __Fc_conv_f, __Fc_conv_i, __Fi_conv_c
! __Fc_conv_d, __Fd_conv_c
!
! __Fc_conv_z
! __Fz_minus, __Fz_add, __Fz_neg
! __Ff_conv_z, __Fz_conv_f, __Fz_conv_i, __Fi_conv_z
! __Fz_conv_d, __Fd_conv_z, __Fz_conv_c

! _c_abs, z_abs, _c_cmplx, _d_cmplx, _r_cnjg, _d_cnjg
! _r_dim, _d_dim, _r_imag, _d_imag, _r_sign, _d_sign

! __Fc_mult, __Fz_mult
! 

!	begin fsqrt[sd] inline expansion templates
!	remove if fsqrt[sd] instructions aren't in hardware

        .inline _Fsqrt,1
        st      %o0,[%sp+0x44]
        ld      [%sp+0x44],%f0
	fsqrts  %f0,%f0
	.end

        .inline _sqrt,2
        std     %o0,[%sp+0x48]          ! store to 8-aligned address
        ldd     [%sp+0x48],%f0
        fsqrtd  %f0,%f0
	.end

        .inline _r_sqrt_,1
        ld      [%o0],%f0
        fsqrts  %f0,%f0
	.end

        .inline _d_sqrt_,1
        ld      [%o0],%f0
        ld      [%o0+4],%f1
        fsqrtd  %f0,%f0
        .end

	.inline	_r_hypot_,2
	ld	[%o0],%o4
	sethi	0x1fffff,%o5
	or	%o5,1023,%o5
	and	%o4,%o5,%o4
	sethi	0x1fe000,%o3
	cmp	%o4,%o3
	bne	2f
	ld	[%o0],%f0	! load result with first argument
	ba	5f		! first argument is inf
	fabss	%f0,%f0
2:		
	ld	[%o1],%o4
	sethi	0x1fffff,%o5
	or	%o5,1023,%o5
	and	%o4,%o5,%o4
	sethi	0x1fe000,%o3
	cmp	%o4,%o3
	bne	4f
	nop
	ld	[%o1],%f0	! second argument inf
	ba	5f
	fabss	%f0,%f0
4:
	fstod	%f0,%f0
	ld	[%o1],%f3
	fmuld	%f0,%f0,%f0
	fstod	%f3,%f2
	fmuld	%f2,%f2,%f2
	faddd	%f2,%f0,%f0
	fsqrtd	%f0,%f0
	fdtos	%f0,%f0
5:
	.end

	.inline	_c_abs,1
	ld	[%o0],%o4
	sethi	0x1fffff,%o5
	or	%o5,1023,%o5
	and	%o4,%o5,%o4
	sethi	0x1fe000,%o3
	cmp	%o4,%o3
	bne	2f
	ld	[%o0],%f0
	ba	5f
	fabss	%f0,%f0
2:		
	ld	[%o0+4],%o4
	sethi	0x1fffff,%o5
	or	%o5,1023,%o5
	and	%o4,%o5,%o4
	sethi	0x1fe000,%o3
	cmp	%o4,%o3
	bne	4f
	nop
	ld	[%o0+4],%f0
	ba	5f
	fabss	%f0,%f0
! store to 8-aligned address
4:
	fstod	%f0,%f0
	ld	[%o0+4],%f3
	fmuld	%f0,%f0,%f0
	fstod	%f3,%f2
	fmuld	%f2,%f2,%f2
	faddd	%f2,%f0,%f0
	fsqrtd	%f0,%f0
	fdtos	%f0,%f0
5:
	.end

!	remove if fsqrt[sd] instructions aren't in hardware
!	end fsqrt[sd] inline expansion templates

! alternate definition for those who don't want fsqrt instructions
	.inline	_c_abs,1
	add	%o0,4,%o1
	call	_r_hypot_,2
	nop
	.end

	.inline	_min_subnormal,0
	set	0x0,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	set	0x1,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f1
	.end

	.inline	_d_min_subnormal_,0
	set	0x0,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	set	0x1,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f1
	.end

	.inline	_r_min_subnormal_,0
	set	0x1,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	.end

	.inline	_max_subnormal,0
	set	0x000fffff,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	set	0xffffffff,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f1
	.end

	.inline	_d_max_subnormal_,0
	set	0x000fffff,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	set	0xffffffff,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f1
	.end

	.inline	_r_max_subnormal_,0
	set	0x007fffff,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	.end

	.inline	_min_normal,0
	set	0x00100000,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	set	0x0,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f1
	.end

	.inline	_d_min_normal_,0
	set	0x00100000,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	set	0x0,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f1
	.end

	.inline	_r_min_normal_,0
	set	0x00800000,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	.end

	.inline	_max_normal,0
	set	0x7fefffff,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	set	0xffffffff,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f1
	.end

	.inline	_d_max_normal_,0
	set	0x7fefffff,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	set	0xffffffff,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f1
	.end

	.inline	_r_max_normal_,0
	set	0x7f7fffff,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	.end

	.inline	___infinity,0
        set      0x7ff00000,%o0
        set      0x0,%o1
        std      %o0,[%sp+0x48]
        ldd      [%sp+0x48],%f0
        .end

	.inline	_infinity,0
        set      0x7ff00000,%o0
        set      0x0,%o1
        std      %o0,[%sp+0x48]
        ldd      [%sp+0x48],%f0
        .end

	.inline	_d_infinity_,0
	set	0x7ff00000,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	set	0x0,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f1
	.end

	.inline	_r_infinity_,0
	set	0x7f800000,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	.end

	.inline	_signaling_nan,0
	set	0x7ff00000,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	set	0x1,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f1
	.end

	.inline	_d_signaling_nan_,0
	set	0x7ff00000,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	set	0x1,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f1
	.end

	.inline	_r_signaling_nan_,0
	set	0x7f800001,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	.end

	.inline	_quiet_nan,0
	set	0x7fffffff,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	set	0xffffffff,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f1
	.end

	.inline	_d_quiet_nan_,0
	set	0x7fffffff,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	set	0xffffffff,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f1
	.end

	.inline	_r_quiet_nan_,0
	set	0x7fffffff,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	.end

	.inline	__swapEX,1
	set     _fp_accrued_exceptions,%o3
	st      %o0,[%o3]
	and     %o0,0x1f,%o1
	sll     %o1,5,%o1               ! shift input to aexc bit location
	st      %fsr,[%sp+0x44]
	ld      [%sp+0x44],%o0          ! o0 = fsr
	andn    %o0,0x3e0,%o2
	or      %o1,%o2,%o1             ! o1 = new fsr
	st      %o1,[%sp+0x44]
	ld      [%sp+0x44],%fsr
	srl     %o0,5,%o0
	and     %o0,0x1f,%o0
	.end

	.inline	__swapRD,1
	set     _fp_direction,%o3
	and	%o0,0x3,%o0
	st      %o0,[%o3]
	sll     %o0,30,%o1              ! shift input to RD bit location
	st      %fsr,[%sp+0x44]
	ld      [%sp+0x44],%o0          ! o0 = fsr
	set     0xc0000000,%o4          ! mask of rounding direction bits
	andn    %o0,%o4,%o2
	or      %o1,%o2,%o1             ! o1 = new fsr
	st      %o1,[%sp+0x44]
	ld      [%sp+0x44],%fsr
	srl     %o0,30,%o0
	and     %o0,0x3,%o0
	.end

	.inline	__swapRP,1
	set     _fp_precision,%o3
	and	%o0,0x3,%o0
	st      %o0,[%o3]
	sll     %o0,28,%o1              ! shift input to RP bit location
	st      %fsr,[%sp+0x44]
	ld      [%sp+0x44],%o0          ! o0 = fsr
	set     0x30000000,%o4          ! mask of rounding precision bits
	andn    %o0,%o4,%o2
	or      %o1,%o2,%o1             ! o1 = new fsr
	st      %o1,[%sp+0x44]
	ld      [%sp+0x44],%fsr
	srl     %o0,28,%o0
	and     %o0,0x3,%o0
	.end

	.inline	__swapTE,1
	and	%o0,0x1f,%o0
	sll     %o0,23,%o1              ! shift input to TEM bit location
	st      %fsr,[%sp+0x44]
	ld      [%sp+0x44],%o0            ! o0 = fsr
	set     0x0f800000,%o4          ! mask of TEM (Trap Enable Mode bits)
	andn    %o0,%o4,%o2
	or      %o1,%o2,%o1             ! o1 = new fsr
	st      %o1,[%sp+0x48]
	ld      [%sp+0x48],%fsr
	srl     %o0,23,%o0
	and     %o0,0x1f,%o0
	.end

	.inline	_fp_class,2
	sethi	%hi(0x80000000),%o2
	andn	%o0,%o2,%o0
	orcc	%o0,%o1,%g0
	bne	1f
	sethi	%hi(0x7ff00000),%o2
	ba	2f			! x is 0
	mov	0,%o0
1:	andcc	%o0,%o2,%g0
	bne	1f
	cmp	%o0,%o2
	ba	2f			! x is subnormal
	mov	1,%o0
1:	bge	1f
	andn	%o0,%o2,%o0
	ba	2f			! x is normal
	mov	2,%o0
1:	orcc	%o0,%o1,%g0
	bne	1f
	sethi	%hi(0x00080000),%o2
	ba	2f			! x is infinity
	mov	3,%o0
1:	andcc	%o0,%o2,%g0
	bne	2f
	mov	4,%o0			! x is quiet NaN
	mov	5,%o0			! x is signaling NaN
2:
	.end

	.inline	_ir_fp_class,1
	ld	[%o0],%o0
	sethi	%hi(0x80000000),%o2
	andncc	%o0,%o2,%o0
	bne	1f
	sethi	%hi(0x7f800000),%o2
	ba	2f			! x is 0
	mov	0,%o0
1:	andcc	%o0,%o2,%g0
	bne	1f
	cmp	%o0,%o2
	ba	2f			! x is subnormal
	mov	1,%o0
1:	bge	1f
	andn	%o0,%o2,%o0
	ba	2f			! x is normal
	mov	2,%o0
1:	bg	1f
	sethi	%hi(0x00400000),%o2
	ba	2f			! x is infinity
	mov	3,%o0
1:	andcc	%o0,%o2,%g0
	bne	2f
	mov	4,%o0			! x is quiet NaN
	mov	5,%o0			! x is signaling NaN
2:
	.end

	.inline	_copysign,4
        set     0x80000000,%o3
        and     %o2,%o3,%o2
        andn    %o0,%o3,%o0
        or      %o0,%o2,%o0
        std      %o0,[%sp+0x48]
        ldd     [%sp+0x48],%f0
        .end

	.inline	_r_copysign_,2
	ld	[%o0],%o0
	ld	[%o1],%o1
	set	0x80000000,%o2
	andn	%o0,%o2,%o0
	and	%o1,%o2,%o1
	or	%o0,%o1,%o0
	st	%o0,[%sp+0x44]
	ld	[%sp+0x44],%f0
	.end

	.inline	_finite,2
	set	0x7ff00000,%o1
	and	%o0,%o1,%o0
	cmp	%o0,%o1
	bne	1f
	mov	1,%o0
	mov	0,%o0
1:
	.end

	.inline	_ir_finite_,1
	ld	[%o0],%o0
	set	0x7f800000,%o1
	and	%o0,%o1,%o0
	cmp	%o0,%o1
	bne	1f
	mov	1,%o0
	mov	0,%o0
1:
	.end

	.inline	_signbit,1
	srl	%o0,31,%o0
	.end

	.inline	_ir_signbit_,1
	ld	[%o0],%o0
	srl	%o0,31,%o0
	.end

	.inline	_ir_isinf_,1		! used in r_hypot_
	ld	[%o0],%o0		
	sethi	%hi(0x7fffffff),%o1
	or	%o1,%lo(0x7fffffff),%o1	! [internal]
	and	%o0,%o1,%o0
	sethi	%hi(0x7f800000),%o3
	cmp	%o0,%o3
	bne,a	1f
	mov	0,%o0
	mov	1,%o0
1:
	.end

	.inline	_isinf,2
	tst	%o1
	bne	1f
	sethi	%hi(0x80000000),%o2
	andn	%o0,%o2,%o0
	sethi	%hi(0x7ff00000),%o2
	cmp	%o0,%o2
	be	2f
	mov	1,%o0
1:
	mov	0,%o0
2:
	.end

	.inline	_isnan,2
	sethi	%hi(0x7ff00000),%o2
	and	%o0,%o2,%o3
	cmp	%o3,%o2
	bne	1f
	sethi	%hi(0xfff00000),%o2
	andn	%o0,%o2,%o0
	orcc	%o0,%o1,%g0
	bne	2f
	mov	1,%o0
1:
	mov	0,%o0
2:
	.end

	.inline	_isnormal,2
	sethi	%hi(0x80000000),%o2
	andn	%o0,%o2,%o0
	sethi	%hi(0x7ff00000),%o2
	cmp	%o0,%o2
	bge	1f
	sethi	%hi(0x00100000),%o2
	cmp	%o0,%o2
	bge	2f
	mov	1,%o0
1:
	mov	0,%o0
2:
	.end

	.inline	_issubnormal,2
	sethi	%hi(0x80000000),%o2
	andn	%o0,%o2,%o0
	sethi	%hi(0x00100000),%o2
	cmp	%o0,%o2
	bge	1f
	orcc	%o0,%o1,%g0
	bne	2f
	mov	1,%o0
1:
	mov	0,%o0
2:
	.end

	.inline	_iszero,2
	sethi	%hi(0x80000000),%o2
	andn	%o0,%o2,%o0
	orcc	%o0,%o1,%g0
	be	1f
	mov	1,%o0
	mov	0,%o0
1:
	.end

        .inline _abs,1          /* integer abs */
        subcc   %g0,%o0,%g0     /* compute 0-o0 */
        ble     1f              /* nop if 0 <= o0 */
        nop
        sub     %g0,%o0,%o0     /* o0 := -o0 */
1:
        .end

	.inline	_fabs,2
        sll     %o0,1,%o0
        srl     %o0,1,%o0
        std     %o0,[%sp+0x48]
        ldd     [%sp+0x48],%f0
	.end

	.inline	_r_fabs_,1
	ld	[%o0],%f0
	fabss	%f0,%f0
	.end

!
! _Facos, _Faint, _Fanint, _Fasin, _Fatan, _Fcos, _Fcosh, _Fexp, _Fexp10
! _Fexp2, _Flog, _Flog10, _Fnint, _Fsin, _Fsinh, _Ftan, _Ftanh
!
	.inline	_Facos,1
	st	%o0,[%sp+0x44]
	add	%sp,0x44,%o0
	call	_r_acos_,1
	nop