📄 startup.s
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;******************************************************************************
; File: startup.s
; Discription: Startup code
; Copyright:
; Author: houwb
;******************************************************************************
IMPORT |Image$$RO$$Base|
IMPORT |Image$$RO$$Limit|
IMPORT |Image$$RW$$Base|
IMPORT |Image$$RW$$Limit|
IMPORT |Image$$ZI$$Base|
IMPORT |Image$$ZI$$Limit|
IMPORT sys_init
IMPORT shell
IMPORT __main
IMPORT OS_CPU_IRQ_ISR
IMPORT OS_CPU_FIQ_ISR
IMPORT do_irq
IMPORT do_fiq
;******************************************************************************
; Vector Table
;******************************************************************************
CODE32
AREA STARTUP,CODE,READONLY
GET settings.s ;Get system default settings
ENTRY
start
LDR PC, reset_entry
LDR PC, undefined_entry
LDR PC, swi_entry
LDR PC, prefetch_abort_entry
LDR PC, data_abort_entry
NOP
LDR PC, irq_entry
LDR PC, fiq_entry
reset_entry DCD sys_reset
undefined_entry DCD undefined
swi_entry DCD software_interrupt
prefetch_abort_entry DCD prefetch_abort
data_abort_entry DCD data_abort
no_use DCD 0
irq_entry DCD OS_CPU_IRQ_ISR ;irq_handler
fiq_entry DCD OS_CPU_FIQ_ISR ;fiq_handler
;******************************************************************************
; Exception handler
;******************************************************************************
undefined
B undefined
software_interrupt
B software_interrupt
prefetch_abort
B prefetch_abort
data_abort
B data_abort
;******************************************************************************
; Interrupt handler
; Note: not used in ucos mode
;******************************************************************************
irq_handler
STMFD SP!, {R0-R3, R12, LR}
BL do_irq
LDMFD SP!, {R0-R3, R12, LR}
SUBS PC, LR, #4
fiq_handler
STMFD SP!, {R0-R3, R12, LR}
BL do_fiq
LDMFD SP!, {R0-R3, R12, LR}
SUBS PC, LR, #4
;******************************************************************************
; Function: sys_reset
; Discription: reset the value of the system
; manager registers and init stack
; Entry: none
; Return: none
;******************************************************************************
sys_reset
;******************************************************************************
;disable all interrupts
MSR CPSR_c, #MOD_SVC:OR:BIT_I:OR:BIT_F ;Disable all interrupts
LDR r2, =aINTMSK ;R2->interrupt controller
MVN R1, #0 ;&FFFFFFFF
STR R1, [R2] ;disable all interrupt soucres
LDR R2, =aINTPND ;R2->interrupt pend register.
MVN R1, #0 ;&FFFFFFFF
STR R1, [R2]
;******************************************************************************
;Initialize sys config registers
LDR R0, =aSYSCFG
LDR R1, =vSYSCFG
STR R1, [R0, #0]
LDR R0, =aEXTACON0
LDR R1, =vEXTACON0
STR R1, [R0, #0]
LDR R0, =aEXTACON1
LDR R1, =vEXTACON1
STR R1, [R0, #0]
;******************************************************************************
;Initalize the memory as follows:
; FLASH @ 0x000000 ~ 0x080000
; SDRAM @ 0x080000 ~ 0x480000
LDR R0, =aEXTDBWTH
LDR R1, =vEXTDBWTH
LDR R2, =vROMCON0
LDR R3, =vROMCON1
LDR R4, =vROMCON2
LDR R5, =vROMCON3
LDR R6, =vROMCON4
LDR R7, =vROMCON5
LDR R8, =vDRAMCON0
LDR R9, =vDRAMCON1
LDR R10, =vDRAMCON2
LDR R11, =vDRAMCON3
LDR R12, =vREFEXTCON
;STMIA R0, {R1-R12}
;******************************************************************************
;copy flash to sdram
LDR R0, =|Image$$RO$$Base|
LDR R1, =|Image$$RO$$Limit|
LDR R2, =|Image$$RW$$Base|
LDR R3, =|Image$$ZI$$Base|
SUB R1, R1, R0
SUB R3, R3, R2
ADD R2, R1, R3 ;IMAGE SIZE
LDR R1, =(DRAMBase_DRC0:SHL:6) ;SDRAM BASE
0
;LDR R3, [R0], #4
;STR R3, [R1], #4
;SUBS R2, R2, #4
;BNE %B0
;******************************************************************************
;Remap the memory
; FLASH @ 0x400000 ~ 0x480000
; SDRAM @ 0x000000 ~ 0x400000
LDR R0, =aEXTDBWTH
LDR R1, =vEXTDBWTH
LDR R2, =vROMCON0_REMAP
LDR R3, =vROMCON1_REMAP
LDR R4, =vROMCON2_REMAP
LDR R5, =vROMCON3_REMAP
LDR R6, =vROMCON4_REMAP
LDR R7, =vROMCON5_REMAP
LDR R8, =vDRAMCON0_REMAP
LDR R9, =vDRAMCON1_REMAP
LDR R10, =vDRAMCON2_REMAP
LDR R11, =vDRAMCON3_REMAP
LDR R12, =vREFEXTCON
STMIA R0, {R1-R12}
;******************************************************************************
; Initialize Stacks
BL init_stack
;******************************************************************************
; Copy RW & ZI to SDRAM
LDR R0, =|Image$$RO$$Limit|
LDR R1, =|Image$$RW$$Base|
LDR R3, =|Image$$ZI$$Base|
CMP R0, R1
BEQ %F2
1 CMP R1, R3 ; Copy init data
LDRCC R2, [R0], #4
STRCC R2, [R1], #4
BCC %B1
2 LDR R1, =|Image$$ZI$$Limit| ; Top of zero init segment
MOV R2, #0
3 CMP R3, R1 ; Zero init
STRCC R2, [R3], #4
BCC %B3
;******************************************************************************
; Goto C Code
BL sys_init
BL shell
BL __main
B .
;******************************************************************************
; Function: init_stack
; Discription: Initialize stack
; Entry: none
; Return: none
;******************************************************************************
init_stack
MOV R0, LR
LDR R1, =|Image$$ZI$$Limit|
;setup irq mode stack
MSR CPSR_c, #MOD_IRQ:OR:BIT_I:OR:BIT_F ;disable interrupt
ADD R1, R1, #IRQ_STACK_SIZE
BIC R1, R1, #0x03
MOV SP, R1
;setup fiq mode stack
MSR CPSR_c, #MOD_FIQ:OR:BIT_I:OR:BIT_F
ADD R1, R1, #FIQ_STACK_SIZE
BIC R1, R1, #0x03
MOV SP, R1
;setup abt mode stack
MSR CPSR_c, #MOD_ABT:OR:BIT_I:OR:BIT_F
ADD R1, R1, #ABT_STACK_SIZE
BIC R1, R1, #0x03
MOV SP, R1
;setup und mode stack
MSR CPSR_c, #MOD_UND:OR:BIT_I:OR:BIT_F
ADD R1, R1, #UND_STACK_SIZE
BIC R1, R1, #0x03
MOV SP, R1
;setup usr mode stack
MSR CPSR_c, #MOD_SYS:OR:BIT_I:OR:BIT_F
ADD R1, R1, #USR_STACK_SIZE
BIC R1, R1, #0x03
MOV SP, R1
;setup svc mode stack
MSR CPSR_c, #MOD_SVC:OR:BIT_I:OR:BIT_F
ADD R1, R1, #SVC_STACK_SIZE
BIC R1, R1, #0x03
MOV SP, R1
;MSR CPSR_c, #MOD_SYS ;enable interrupt
MOV PC, R0
;******************************************************************************
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