📄 smodel.mdl
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Model {
Name "smodel"
Version 5.0
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ExecutionOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip on
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Wed Dec 22 21:23:03 1999"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "wangjun"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Sun Nov 17 17:14:05 2002"
ModelVersionFormat "1.%<AutoIncrement:6>"
ConfigurationManager "none"
SimParamPage "Solver"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "oneshot"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect off
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "ode45"
SolverMode "Auto"
StartTime "0.0"
StopTime "10.0"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints off
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
RTWInlineParameters off
BlockReductionOpt on
BooleanDataType off
ConditionallyExecuteInputs on
ParameterPooling on
OptimizeBlockIOStorage on
ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Abs
SaturateOnIntegerOverflow on
ZeroCross on
}
Block {
BlockType Clock
DisplayTime off
}
Block {
BlockType Integrator
ExternalReset "none"
InitialConditionSource "internal"
InitialCondition "0"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
ZeroCross on
}
Block {
BlockType Outport
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType Step
Time "1"
Before "0"
After "1"
SampleTime "-1"
VectorParams1D on
ZeroCross on
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType TransferFcn
Numerator "[1]"
Denominator "[1 2 1]"
AbsoluteTolerance "auto"
Realization "auto"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "smodel"
Location [102, 79, 602, 223]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Abs
Name "Abs"
Position [230, 35, 260, 65]
Port {
PortNumber 1
Name "|e|"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
}
Block {
BlockType Clock
Name "Clock"
Position [245, 85, 265, 105]
Decimation "10"
}
Block {
BlockType TransferFcn
Name "G(s)"
Position [90, 32, 150, 68]
Denominator "[1 a 1]"
Port {
PortNumber 1
Name "y"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
}
Block {
BlockType Integrator
Name "Integrator"
Ports [1, 1]
Position [370, 45, 400, 75]
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [300, 42, 330, 73]
Port {
PortNumber 1
Name "t|e|"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
}
Block {
BlockType Step
Name "Step"
Position [30, 35, 60, 65]
Time "0"
SampleTime "0"
Port {
PortNumber 1
Name "u"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [180, 40, 200, 60]
ShowName off
IconShape "round"
Inputs "|+-"
Port {
PortNumber 1
Name "e"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
}
Block {
BlockType Outport
Name "Out1"
Position [430, 53, 460, 67]
}
Line {
Name "e"
Labels [0, 0]
SrcBlock "Sum"
SrcPort 1
DstBlock "Abs"
DstPort 1
}
Line {
Name "|e|"
Labels [0, 0]
SrcBlock "Abs"
SrcPort 1
DstBlock "Product"
DstPort 1
}
Line {
Name "t|e|"
Labels [1, 0]
SrcBlock "Product"
SrcPort 1
DstBlock "Integrator"
DstPort 1
}
Line {
Name "y"
Labels [0, 0]
SrcBlock "G(s)"
SrcPort 1
DstBlock "Sum"
DstPort 1
}
Line {
SrcBlock "Clock"
SrcPort 1
Points [15, 0]
DstBlock "Product"
DstPort 2
}
Line {
SrcBlock "Integrator"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
Name "u"
SrcBlock "Step"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "G(s)"
DstPort 1
}
Branch {
Labels [3, 1]
Points [0, 35; 120, 0]
DstBlock "Sum"
DstPort 2
}
}
}
}
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