📄 regst9.inc
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oev equ 02h ; on chip event bit on OVF/UDF mask
ou_set equ 00h ; overflow underflow set mask
ou_tog equ 04h ; overflow underflow toggle mask
ou_res equ 08h ; overflow underflow reset mask
ou_nop equ 0Ch ; overflow underflow nop mask
c1_set equ 00h ; Compare 1 set mask
c1_tog equ 10h ; Compare 1 toggle mask
c1_res equ 20h ; Compare 1 reset mask
c1_nop equ 30h ; Compare 1 nop mask
c0_set equ 00h ; Compare 0 set mask
c0_tog equ 40h ; Compare 0 toggle mask
c0_res equ 80h ; Compare 0 reset mask
c0_nop equ 0C0h ; Compare 0 nop mask
T_FLAGR reg R254 ; MFTimer Flags Register.
__defbit T_ao,T_FLAGR,0 ; and/or on capture interrupt
__defbit T_ocm0,T_FLAGR,1 ; overrun compare 0
__defbit T_ocp0,T_FLAGR,2 ; overrun capture 0
__defbit T_ouf,T_FLAGR,3 ; overflow underflow flag
__defbit T_cm1,T_FLAGR,4 ; successful compare 1
__defbit T_cm0,T_FLAGR,5 ; successful compare 0
__defbit T_cp1,T_FLAGR,6 ; successful capture 1
__defbit T_cp0,T_FLAGR,7 ; successful capture 0
T_IDMR equ R255 ; MFTimer Interrupt DMA Mask Register.
__defbit T_oui,T_IDMR,0 ; overflow underflow interrupt
__defbit T_cm1i,T_IDMR,1 ; Compare 1 interrupt
__defbit T_cm0i,T_IDMR,2 ; Compare 0 interrupt
__defbit T_cm0d,T_IDMR,3 ; Compare 0 DMA
__defbit T_cp1i,T_IDMR,4 ; Capture 1 interrupt
__defbit T_cp0i,T_IDMR,5 ; Capture 0 interrupt
__defbit T_cp0d,T_IDMR,6 ; Capture 0 DMA
__defbit T_gtien,T_IDMR,7 ; global timer interrupt enable
T0_DCPR reg R240 ; MFTimer 0 DMA Counter Pointer Register.
T1_DCPR reg R244 ; MFTimer 1 DMA Counter Pointer Register.
T0_DAPR reg R241 ; MFTimer 0 DMA Address Pointer Register.
T1_DAPR reg R245 ; MFTimer 1 DMA Address Pointer Register.
T0_IVR reg R242 ; MFTimer 0 Interrupt Vector Register.
T1_IVR reg R246 ; MFTimer 1 Interrupt Vector Register.
T0_IDCR reg R243 ; MFTimer 0 Interrupt/DMA Control Register.
T1_IDCR reg R247 ; MFTimer 1 Interrupt/DMA Control Register.
T2_DCPR reg R240 ; MFTimer 2 DMA Counter Pointer Register.
T3_DCPR reg R244 ; MFTimer 3 DMA Counter Pointer Register.
T2_DAPR reg R241 ; MFTimer 2 DMA Address Pointer Register.
T3_DAPR reg R245 ; MFTimer 3 DMA Address Pointer Register.
T2_IVR reg R242 ; MFTimer 2 Interrupt Vector Register.
T3_IVR reg R246 ; MFTimer 3 Interrupt Vector Register.
T2_IDCR reg R243 ; MFTimer 2 Interrupt/DMA Control Register.
T3_IDCR reg R247 ; MFTimer 3 Interrupt/DMA Control Register.
plm equ 07h ; Priority level mask
swen equ 08h ; Swap function enable mask
dctd equ 10h ; DMA compare transaction destination mask
dcts equ 20h ; DMA capture transaction source mask
cme equ 40h ; Compare 0 end of block mask
cpe equ 80h ; Capture 0 end of block mask
T_IOCR reg R248 ; MFTimer I/O connection register
sc0 equ 01h ; TxOUTA and TxINA connection bit (even)
sc1 equ 02h ; TxOUTA and TxINA connection bit (odd)
;----------------------------------------------------------------------------
; A/D-Wandler
if MOMCPUNAME<>"ST9020"
AD0_PG equ 63 ; A/D converter registers page
AD1_PG equ 62 ; second A/D unit
AD_D0R reg R240 ; Channel 0 data register
AD_D1R reg R241 ; Channel 1 data register
AD_D2R reg R242 ; Channel 2 data register
AD_D3R reg R243 ; Channel 3 data register
AD_D4R reg R244 ; Channel 4 data register
AD_D5R reg R245 ; Channel 5 data register
AD_D6R reg R246 ; Channel 6 data register
AD_D7R reg R247 ; Channel 7 data register
AD_LT6R reg R248 ; Channel 6 lower threshold register
AD_LT7R reg R249 ; Channel 7 lower threshold register
AD_UT6R reg R250 ; Channel 6 upper threshold register
AD_UT7R reg R251 ; Channel 7 upper threshold register
AD_CRR reg R252 ; Compare result register
__defbit AD_c6l,AD_CRR,4 ; Compare channel 6 lower bit
__defbit AD_c7l,AD_CRR,5 ; Compare channel 7 lower bit
__defbit AD_c6u,AD_CRR,6 ; Compare channel 6 upper bit
__defbit AD_c7u,AD_CRR,7 ; Compare channel 7 upper bit
AD_CLR reg R253 ; Control logic register
__defbit AD_st,AD_CLR,0 ; start/stop bit
__defbit AD_cont,AD_CLR,1 ; Continuous mode
__defbit AD_pow,AD_CLR,2 ; power up/down control
__defbit AD_intg,AD_CLR,3 ; internal trigger
__defbit AD_extg,AD_CLR,4 ; External trigger
sch equ 0E0h ; scan channel selection mask
AD_ICR reg R254 ; interrupt control register
__defbit AD_awdi,AD_ICR,4 ; analog watch-dog interrupt
__defbit AD_eci,AD_ICR,5 ; End of count interrupt
__defbit AD_awd,AD_ICR,6 ; analog watch-dog pending flag
__defbit AD_ecv,AD_ICR,7 ; End of conversion pending flag
AD_prl equ 07h ; priority level mask
AD_IVR reg R255 ; interrupt vector register
endif
;----------------------------------------------------------------------------
; Serielle Schnittstelle
SCI1_PG equ 24 ; SCI1 control registers page
SCI2_PG equ 25 ; SCI2 control registers page
SCI3_PG equ 26 ; SCI3 control registers page
SCI4_PG equ 27 ; SCI4 control registers page
S_RDCPR reg R240 ; receive DMA counter pointer register
S_RDAPR reg R241 ; receive DMA address pointer register
S_TDCPR reg R242 ; transmit DMA counter pointer register
S_TDAPR reg R243 ; transmit DMA address pointer register
S_IVR reg R244 ; interrupt vector register
S_ACR reg R245 ; address compare register
S_IMR reg R246 ; interrupt mask register
__defbit S_txdi,S_IMR,0 ; transmitter data interrupt
__defbit S_rxdi,S_IMR,1 ; receiver data interrupt
__defbit S_rxb,S_IMR,2 ; receiver break
__defbit S_rxa,S_IMR,3 ; receiver address
__defbit S_rxe,S_IMR,4 ; receiver error
__defbit S_txeob,S_IMR,5 ; transmit end of block
__defbit S_rxeob,S_IMR,6 ; receive end of block
__defbit S_hsn,S_IMR,7 ; Holding or shift register empty.
S_ISR reg R247 ; interrupt status register
__defbit S_txsem,S_ISR,0 ; transmit shift register empty
__defbit S_txhem,S_ISR,1 ; transmit hold register empty
__defbit S_rxdp,S_ISR,2 ; received data pending bit
__defbit S_rxbp,S_ISR,3 ; received break pending bit
__defbit S_rxap,S_ISR,4 ; received address pending bit
__defbit S_pe,S_ISR,5 ; parity error pending bit
__defbit S_fe,S_ISR,6 ; framing error pending bit
__defbit S_oe,S_ISR,7 ; overrun error pending bit
S_RXBR reg R248 ; receive buffer register
S_TXBR reg R248 ; transmit buffer register
S_IDPR reg R249 ; interrupt/DMA priority register
__defbit S_txd,S_IDPR,3 ; transmitter DMA
__defbit S_rxd,S_IDPR,4 ; receiver DMA
__defbit S_sa,S_IDPR,5 ; set address
__defbit S_sb,S_IDPR,6 ; set break
__defbit S_amen,S_IDPR,7 ; address mode enable
S_pri equ 07h ; interrupt/DMA priority mask
S_CHCR reg R250 ; Character configuration register
wl5 equ 000h ; 5 bits data word mask
wl6 equ 001h ; 6 bits data word mask
wl7 equ 002h ; 7 bits data word mask
wl8 equ 003h ; 8 bits data word mask
sb10 equ 000h ; 1.0 stop bit mask
sb15 equ 004h ; 1.5 stop bit mask
sb20 equ 008h ; 2.0 stop bit mask
sb25 equ 00Ch ; 2.5 stop bit mask
ab equ 010h ; address bit insertion mask
pen equ 020h ; parity enable mask
ep equ 040h ; Even parity mask
oddp equ 000h ; odd parity mask
am equ 080h ; address mode mask
S_CCR reg R251 ; Clock configuration register
__defbit S_stpen,S_CCR,0 ; stick parity enable
__defbit S_lben,S_CCR,1 ; loop back enable
__defbit S_aen,S_CCR,2 ; auto echo enable
__defbit S_cd,S_CCR,3 ; Clock divider
__defbit S_xbrg,S_CCR,4 ; External baud rate generator source
__defbit S_xrx,S_CCR,5 ; External receiver source
__defbit S_oclk,S_CCR,6 ; output clock selection
__defbit S_txclk,S_CCR,7 ; transmit clock selection
S_BRGR reg RR252 ; baud rate generator register
S_BRGHR reg R252 ; baud rate generator reg. high
S_BRGLR reg R253 ; baud rate generator reg. low
;----------------------------------------------------------------------------
; Security Register:
SEC_PG equ 59 ; Security register page
SECR reg R255
__defbit tlck,SECR,0 ; test lock bit
__defbit wf1,SECR,1 ; write fuse 1 bit
__defbit hlck,SECR,2 ; hardware lock bit
__defbit wf2,SECR,3 ; write fuse 2 bit
__defbit f2tst,SECR,4 ; select fuse 2 bit
__defbit slck,SECR,7 ; software lock bit
;----------------------------------------------------------------------------
endif
restore ; Listing wieder an
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