📄 regst9.inc
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pmwc4 equ wpm2 ; 4 wait cycles on Prog M.
pmwc5 equ wpm2|wpm0 ; 5 wait cycles on Prog M.
pmwc6 equ wpm2|wpm1 ; 6 wait cycles on Prog M.
pmwc7 equ wpm2|wpm1|wpm0 ; 7 wait cycles on Prog M.
;----------------------------------------------------------------------------
; SPI
SPI_PG equ 0 ; SPI register page
SPIDR reg R253 ; SPI Data register
SPICR reg R254 ; SPI Control register
__defbit SP_spen,SPICR,7 ; Serial Peripheral Enable.
__defbit SP_bms,SPICR,6 ; SBUS/I2C bus Mode Selector.
__defbit SP_arb,SPICR,5 ; Arbitration flag bit.
__defbit SP_busy,SPICR,4 ; SPI busy flag.
__defbit SP_cpol,SPICR,3 ; SPI transmission clock polarity
__defbit SP_cpha,SPICR,2 ; SPI transmission clock phase
__defbit SP_spr1,SPICR,1 ; SPI rate bit 1
__defbit SP_spr0,SPICR,0 ; SPI rate bit 0
SP_8 equ 0 ; SPI clock divider 8 = 1500 kHz (12MHz)
SP_16 equ 1 ; SPI clock divider 16 = 750 kHz (12MHz)
SP_128 equ 2 ; SPI clock divider 128 = 93.75 kHz (12MHz)
SP_256 equ 3 ; SPI clock divider 256 = 46.87 kHz (12MHz)
RW_PG equ 0 ; R/W signal programming page
;----------------------------------------------------------------------------
; Read/Write Register
if MOMCPUNAME="ST9050"
RWR reg R255 ; R/W signal programming register
__defbit RW_rw,RWR,0 ; R/W bit
__defbit RW_bs,RWR,1 ; Bank switch port timing
endif
;----------------------------------------------------------------------------
; Ports
P0C_PG equ 2 ; Port 0 control registers page
P0DR reg R224 ; Port 0 data register
P0C0R reg R240 ; Port 0 control register 0
P0C1R reg R241 ; Port 0 control register 1
P0C2R reg R242 ; Port 0 control register 2
P1C_PG equ 2 ; Port 1 control registers page
P1DR reg R225 ; Port 1 data register
P1C0R reg R244 ; Port 1 control register 0
P1C1R reg R245 ; Port 1 control register 1
P1C2R reg R246 ; Port 1 control register 2
P2C_PG equ 2 ; Port 2 control registers page
P2DR reg R226 ; Port 2 data register
BS_DSR reg R226 ; Bank Switch data segment register
P2C0R reg R248 ; Port 2 control register 0
BS_DDSR reg R248 ; Bank Switch Data DMA segment register
P2C1R reg R249 ; Port 2 control register 1
BS_PDSR reg R249 ; Bank Switch Program DMA segment Register
P2C2R reg R250 ; Port 2 control register 2
P3C_PG equ 2 ; Port 3 control registers page
P3DR reg R227 ; Port 3 data register
BS_PSR reg R227 ; Bank Switch Program Segment Register
P3C0R reg R252 ; Port 3 control register 0
P3C1R reg R253 ; Port 3 control register 1
P3C2R reg R254 ; Port 3 control register 2
P4C_PG equ 3 ; Port 4 control registers page
P4DR reg R228 ; Port 4 data register
P4C0R reg R240 ; Port 4 control register 0
P4C1R reg R241 ; Port 4 control register 1
P4C2R reg R242 ; Port 4 control register 2
P5C_PG equ 3 ; Port 5 control registers page
P5DR reg R229 ; Port 5 data register
P5C0R reg R244 ; Port 5 control register 0
P5C1R reg R245 ; Port 5 control register 1
P5C2R reg R246 ; Port 5 control register 2
P6C_PG equ 3 ; Port 6 control registers page
P6D_PG equ 3 ; Port 6 data register page
P6DR reg R251 ; Port 6 data register
P6C0R reg R248 ; Port 6 control register 0
P6C1R reg R249 ; Port 6 control register 1
P6C2R reg R250 ; Port 6 control register 2
P7C_PG equ 3 ; Port 7 control registers page
P7D_PG equ 3 ; Port 7 data register page
P7DR reg R255 ; Port 7 data register
P7C0R reg R252 ; Port 7 control register 0
P7C1R reg R253 ; Port 7 control register 1
P7C2R reg R254 ; Port 7 control register 2
P8C_PG equ 43 ; Port 8 control registers page
P8D_PG equ 43 ; Port 8 data register page
P8DR reg R251 ; Port 8 data register
P8C0R reg R248 ; Port 8 control register 0
P8C1R reg R249 ; Port 8 control register 1
P8C2R reg R250 ; Port 8 control register 2
P9C_PG equ 43 ; Port 9 control registers page
P9D_PG equ 43 ; Port 9 data register page
P9DR reg R255 ; Port 9 data register
P9C0R reg R252 ; Port 9 control register 0
P9C1R reg R253 ; Port 9 control register 1
P9C2R reg R254 ; Port 9 control register 2
HDCTL2R reg R251 ; Port 2 handshake DMA control register
HDCTL3R reg R255 ; Port 3 handshake DMA control register
HDCTL4R reg R243 ; Port 4 handshake DMA control register
HDCTL5R reg R247 ; Port 5 handshake DMA control register
;Handshake DMA control register configuration.
hsdis equ 0E0h ; Handshake disabled mask
hso2 equ 0C0h ; Handshake output 2 lines mask
hso1 equ 040h ; Handshake output 1 line mask
hsi2 equ 0A0h ; Handshake input 2 lines mask
hsi1 equ 020h ; Handshake input 1 line mask
hsb equ 000h ; Handshake bidirectional mask
den equ 000h ; DMA enable mask
ddi equ 010h ; DMA disable mask
ddw equ 000h ; Data direction output mask (write)
ddr equ 008h ; Data direction input mask (read)
dst equ 004h ; DMA strobe on chip event mask
dcp0 equ 000h ; DMA channel capture0 mask
dcm0 equ 002h ; DMA channel compare0 mask
;----------------------------------------------------------------------------
; Multi function timer
T0D_PG equ 10 ; MFTimer 0 data registers page
T0C_PG equ 9 ; MFTimer 0 control registers page
T1D_PG equ 8 ; MFTimer 1 data registers page
T1C_PG equ 9 ; MFTimer 1 control registers page
T2D_PG equ 14 ; MFTimer 2 data registers page
T2C_PG equ 13 ; MFTimer 2 control registers page
T3D_PG equ 12 ; MFTimer 3 data registers page
T3C_PG equ 13 ; MFTimer 3 control registers page
T_REG0R reg RR240 ; MFTimer REG0 load and capture register.
T_REG0HR reg R240 ; Register 0 high register
T_REG0LR reg R241 ; Register 0 low register
T_REG1R reg RR242 ; MFTimer REG1 load constant
T_REG1HR reg R242 ; Register 1 high register
T_REG1LR reg R243 ; Register 1 low register
T_CMP0R reg RR244 ; MFTimer CMP0 store compare constant.
T_CMP0HR reg R244 ; Compare 0 high register
T_CMP0LR reg R245 ; Compare 0 low register
T_CMP1R reg RR246 ; MFTimer CMP1 store compare constant.
T_CMP1HR reg R246 ; Compare 1 high register
T_CMP1LR reg R247 ; Compare 1 low register
T_TCR reg R248 ; MFTimer Control Register.
__defbit T_cs,T_TCR,0 ; Counter status
__defbit T_of0,T_TCR,1 ; over/underflow on CAP on REG0
__defbit T_udcs,T_TCR,2 ; up/down count status
__defbit T_udc,T_TCR,3 ; up/down count
__defbit T_ccl,T_TCR,4 ; Counter clear
__defbit T_ccmp0,T_TCR,5 ; Clear on compare 0
__defbit T_ccp0,T_TCR,6 ; Clear on capture
__defbit T_cen,T_TCR,7 ; Counter enable
T_TMR reg R249 ; MFTimer Mode Register.
__defbit T_co,T_TMR,0 ; Continuous/one shot bit
__defbit T_ren,T_TMR,1 ; retrigger enable bit
__defbit T_eck,T_TMR,2 ; Enable clocking mode bit
__defbit T_rm0,T_TMR,3 ; register 0 mode bit
__defbit T_rm1,T_TMR,4 ; register 1 mode bit
__defbit T_bm,T_TMR,5 ; bivalue mode bit
__defbit T_oe0,T_TMR,6 ; output 0 enable bit
__defbit T_oe1,T_TMR,7 ; output 1 enable bit
T_ICR reg R250 ; MFTimer External Input Control Register.
exb_f equ 01h ; External B falling edge sensitive mask
exb_r equ 02h ; External B rising edge sensitive mask
exb_rf equ 03h ; External B falling and rising edge mask
exa_f equ 04h ; External A falling edge sensitive mask
exa_r equ 08h ; External A rising edge sensitive mask
exa_rf equ 0Ch ; External A falling and rising edge mask
ab_ii equ 00h ; A I/O B I/O mask
ab_it equ 10h ; A I/O B trigger mask
ab_gi equ 20h ; A gate B I/O mask
ab_gt equ 30h ; A gate B trigger mask
ab_ie equ 40h ; A I/O B external clock mask
ab_ti equ 50h ; A trigger B I/O mask
ab_ge equ 60h ; A gate B external clock mask
ab_tt equ 70h ; A trigger B trigger mask
ab_cucd equ 80h ; A clock up B clock down mask
ab_ue equ 90h ; A clock up/down B external clock mask
ab_tutd equ 0A0h ; A trigger up B trigger down mask
ab_ui equ 0B0h ; A up/down clock B I/O mask
ab_aa equ 0C0h ; A autodiscr. B autodiscr. mask
ab_te equ 0D0h ; A trigger B external clock mask
ab_et equ 0E0h ; A external clock B trigger mask
ab_tg equ 0F0h ; A trigger B gate mask
T_PRSR reg R251 ; MFTimer prescaler register
T_OACR reg R252 ; MFTimer Output A Control Register.
cev equ 02h ; on chip event bit on COMPARE 0 mask
T_OBCR reg R253 ; MFTimer Output B Control Register.
op equ 01h ; output preset bit mask
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