📄 regst9.inc
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save
listing off ; kein Listing 乥er diesen File
;****************************************************************************
;* *
;* AS 1.41 - Datei REGST9.INC *
;* *
;* Sinn : enth刲t SFR-, Makro- und Adre醖efinitionen f乺 die ST9-Familie *
;* *
;* letzte 巒derungen : 6. 2.1997 *
;* *
;****************************************************************************
ifndef regst9inc ; verhindert Mehrfacheinbindung
regst9inc equ 1
if (MOMCPUNAME<>"ST9020")&&(MOMCPUNAME<>"ST9030")&&(MOMCPUNAME<>"ST9040")&&(MOMCPUNAME<>"ST9050")
fatal "Falscher Prozessortyp eingestellt: nur ST9020,ST9030,ST9040 oder ST9050 erlaubt!"
endif
if MOMPASS=1
message "ST9-SFR-Definitionen (C) 1997 Alfred Arnold"
endif
;----------------------------------------------------------------------------
; Registerb刵ke
__CNT set 0
rept 16
BK{"\{__CNT}"}0 equ __CNT*2
BK{"\{__CNT}"}1 equ __CNT*2+1
__CNT set __CNT+1
endm
BK_SYS equ BKE0 ; Group system definition
BK_F equ BKF0 ; page register definition
;----------------------------------------------------------------------------
; Definition eines Bits:
; dies nutzt die interne Definition von Bitsymbolen aus: rrrrbbbi
__defbit macro NAME,REG,BITPOS
NAME bit ((REG&15)<<4)+(BITPOS<<1)
{"NAME"}m equ 1<<BITPOS
endm
;----------------------------------------------------------------------------
; Systemgruppe
FCW reg RR230 ; flag and control word
CICR reg R230 ; central interrupt control register
__defbit gcen,CICR,7 ; global counter enable
__defbit tlip,CICR,6 ; top level interrupt pending bit
__defbit tli,CICR,5 ; top level interrupt bit
__defbit ien,CICR,4 ; interrupt enable flag
__defbit iam,CICR,3 ; interrupt arbitration mode
__defbit cpl2,CICR,2 ; current priority level bit 2
__defbit cpl1,CICR,1 ; current priority level bit 1
__defbit cpl0,CICR,0 ; current priority level bit 0
cplm equ cpl2m|cpl1m|cpl0m ; current priority level
FLAGR reg R231 ; flags register
__defbit c,FLAGR,7 ; carry flag
__defbit z,FLAGR,6 ; zero flag
__defbit s,FLAGR,5 ; sign flag
__defbit v,FLAGR,4 ; overflow flag
__defbit d,FLAGR,3 ; decimal adjust flag
__defbit h,FLAGR,2 ; half carry flag
__defbit uf,FLAGR,1 ; user flag 1
__defbit dp,FLAGR,0 ; data/program memory flag
RPP reg RR232 ; register pointer pair
RP0R reg R232 ; register pointer #0
__defbit rp0s,RP0R,2 ; register pointer selector
RP1R reg R233 ; register pointer #1
__defbit rp1s,RP1R,2 ; register pointer selector
PPR reg R234 ; page pointer register
MODER reg R235 ; mode register
__defbit ssp,MODER,7 ; system stack pointer flag (int/ext)
__defbit usp,MODER,6 ; user stack pointer flag (int/ext)
__defbit div2,MODER,5 ; external clock divided by 2
__defbit prs2,MODER,4 ; internal clock prescaling bit 2
__defbit prs1,MODER,3 ; internal clock prescaling bit 1
__defbit prs0,MODER,2 ; internal clock prescaling bit 0
__defbit brqen,MODER,1 ; bus request enable
__defbit himp,MODER,0 ; high impedance enable
prsm equ prs2m|prs1m|prs0m ; internal clock prescaler
USPR reg RR236 ; user stack pointer
USPHR reg R236
USPLR reg R237
SSPR reg RR238 ; system stack pointer
SSPHR reg R238
SSPLR reg R239
;----------------------------------------------------------------------------
; EEPROM
if MOMCPUNAME="ST9040"
EEP_PG equ 0 ; EEPROM register page
EECR reg R241 ; EEPROM control register
__defbit verify,EECR,6 ; EEPROM verify mode
__defbit eestby,EECR,5 ; EEPROM stand-by
__defbit eeien,EECR,4 ; EEPROM interrupt enable
__defbit pllst,EECR,3 ; Parallel write start
__defbit pllen,EECR,2 ; Parallel write enable
__defbit eebusy,EECR,1 ; EEPROM busy
__defbit eewen,EECR,0 ; EEPROM write enable
endif
;----------------------------------------------------------------------------
; Interrupts
EXINT_PG equ 0 ; EXTERNAL interrupt register page
EITR reg R242 ; External interrupt trigger level register
__defbit tea0,EITR,0 ; Trigger Event A0 bit
__defbit tea1,EITR,1 ; Trigger Event A1 bit
__defbit teb0,EITR,2 ; Trigger Event B0 bit
__defbit teb1,EITR,3 ; Trigger Event B1 bit
__defbit tec0,EITR,4 ; Trigger Event C0 bit
__defbit tec1,EITR,5 ; Trigger Event C1 bit
__defbit ted0,EITR,6 ; Trigger Event D0 bit
__defbit ted1,EITR,7 ; Trigger Event D1 bit
EIPR reg R243 ; External interrupt pending register
__defbit ipa0,EIPR,0 ; Interrupt Pending bit Channel A0
__defbit ipa1,EIPR,1 ; Interrupt Pending bit " A1
__defbit ipb0,EIPR,2 ; Interrupt Pending bit " B0
__defbit ipb1,EIPR,3 ; Interrupt Pending bit " B1
__defbit ipc0,EIPR,4 ; Interrupt Pending bit " C0
__defbit ipc1,EIPR,5 ; Interrupt Pending bit " C1
__defbit ipd0,EIPR,6 ; Interrupt Pending bit " D0
__defbit ipd1,EIPR,7 ; Interrupt Pending bit " D1
EIMR reg R244 ; External interrupt mask register
__defbit ima0,EIMR,0 ; Int. A0 bit
__defbit ima1,EIMR,1 ; Int. A1 bit
__defbit imb0,EIMR,2 ; Int. B0 bit
__defbit imb1,EIMR,3 ; Int. B1 bit
__defbit imc0,EIMR,4 ; Int. C0 bit
__defbit imc1,EIMR,5 ; Int. C1 bit
__defbit imd0,EIMR,6 ; Int. D0 bit
__defbit imd1,EIMR,7 ; Int. D1 bit
EIPLR reg R245 ; Ext. interrupt priority level register
EIVR reg R246 ; External interrupt vector register
__defbit ewen,EIVR,0 ; External wait enable
__defbit ia0s,EIVR,1 ; Interrupt A0 selection
__defbit tlis,EIVR,2 ; Top level input selection
__defbit tltev,EIVR,3 ; Top level trigger event
NICR reg R247 ; Nested interrupt control register
__defbit tlnm,NICR,7 ; Top level not maskable
;----------------------------------------------------------------------------
; Watchdog
WDT_PG equ 0 ; Timer Watchdog page
WDTR reg RR248 ; TWD timer constant register.
WDTHR reg R248 ; TWD timer high constant register
WDTLR reg R249 ; TWD timer low constant register
WDTPR reg R250 ; TWD timer prescaler constant register
WDTCR reg R251 ; TWD timer control register
__defbit WD_stsp8,WDTCR,7 ; TWD start stop.
__defbit WD_sc,WDTCR,6 ; TWD single continuous mode.
__defbit WD_inmd1,WDTCR,5 ; Input mode 1
__defbit WD_inmd2,WDTCR,4 ; Input mode 2
__defbit WD_inen,WDTCR,3 ; TWD input section enable/disable.
__defbit WD_outmd,WDTCR,2 ; TWD output mode.
__defbit WD_wrout,WDTCR,1 ; TWD output bit.
__defbit WD_outen,WDTCR,0 ; TWD output enable.
inm_evc equ 0 ; TWD input mode event counter.
inm_g equ 010h ; TWD input mode gated.
inm_t equ 020h ; TWD input mode triggerable.
inm_r equ 030h ; TWD input mode retriggerable.
WCR reg R252 ; Wait control register
__defbit WD_wden,WCR,6 ; TWD timer enable.
wdm2 equ 1 << 5 ; Data Memory Wait Cycle
wdm1 equ 1 << 4
wdm0 equ 1 << 3
wpm2 equ 1 << 2 ; Program Memory Wait Cycle
wpm1 equ 1 << 1
wpm0 equ 1 << 0
dmwc1 equ wdm0 ; 1 wait cycle on Data M.
dmwc2 equ wdm1 ; 2 wait cycles on Data M.
dmwc3 equ wdm1|wdm0 ; 3 wait cycles on Data M.
dmwc4 equ wdm2 ; 4 wait cycles on Data M.
dmwc5 equ wdm2|wdm0 ; 5 wait cycles on Data M.
dmwc6 equ wdm2|wdm1 ; 6 wait cycles on Data M.
dmwc7 equ wdm2|wdm1|wdm0 ; 7 wait cycles on Data M.
pmwc1 equ wpm0 ; 1 wait cycle on Prog M.
pmwc2 equ wpm1 ; 2 wait cycles on Prog M.
pmwc3 equ wpm1|wpm0 ; 3 wait cycles on Prog M.
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