📄 h8_3048.inc
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TIER{Name} equ Base+2 ; Timer interrupt enable register
TSR{Name} equ Base+3 ; Timer status register
TCNT{Name}H equ Base+4 ; Timer counter H
TCNT{Name}L equ Base+5 ; Timer counter L
GRA{Name}H equ Base+6 ; General register A (high)
GRA{Name}L equ Base+7 ; General register A (low)
GRB{Name}H equ Base+8 ; General register B (high)
GRB{Name}L equ Base+9 ; General register B (low)
endm
__deftimer $ff64,"0"
__deftimer $ff6e,"1"
__deftimer $ff78,"2"
__deftimer $ff82,"3"
BRA3H equ $ff8c ; Buffer register A3 (high)
BRA3L equ $ff8d ; Buffer register A3 (low)
BRB3H equ $ff8e ; Buffer register B3 (high)
BRB3L equ $ff8f ; Buffer register B3 (low)
__deftimer $ff82,"4"
BRA4H equ $ff9c ; Buffer register A4 (high)
BRA4L equ $ff9d ; Buffer register A4 (low)
BRB4H equ $ff9e ; Buffer register B4 (high)
BRB4L equ $ff9f ; Buffer register B4 (low)
;TMDR-Register
MDF equ 6 ; Phase counting mode flag
FDIR equ 5 ; Flag direction
PWM4 equ 4 ; PWM mode
PWM3 equ 3
PWM2 equ 2
PWM1 equ 1
PWM0 equ 0
;TFCR-Register
CMD1 equ 5 ; Combination mode
CMD0 equ 4
BFB4 equ 3 ; Buffer mode B4
BFA4 equ 2 ; Buffer mode A4
BFB3 equ 1 ; Buffer mode B3
BFA3 equ 0 ; Buffer mode A3
;TOER-Register
EXB4 equ 5 ; Master enable TOCXB4
EXA4 equ 4 ; Master enable TOCXA4
EB3 equ 3 ; Master enable TIOCB3
EB4 equ 2 ; Master enable TIOCB4
EA4 equ 1 ; Master enable TIOCA4
EA3 equ 0 ; Master enable TIOCA3
;TOCR-Register
XTGD equ 4 ; External trigger disable
OLS4 equ 1 ; Output level select 4
OLS3 equ 0 ; Output level select 3
;TCR-Register
CCLR1 equ 6 ; Counter clear
CCLR0 equ 5
CKEG1 equ 4 ; Counter edge
CKEG0 equ 3
TPSC2 equ 2 ; Timer prescaler
TPSC1 equ 1
TPSC0 equ 0
;TIOR-Register
IOB2 equ 6 ; I/O control B2
IOB1 equ 5 ; I/O control B1
IOB0 equ 4 ; I/O control B0
IOA2 equ 2 ; I/O control A2
IOA1 equ 1 ; I/O control A1
IOA0 equ 0 ; I/O control A0
;TSR-Register
OVF equ 2 ; Overflow flag
IMFB equ 1 ; Input capture / compare match flag B
IMFA equ 0 ; Input capture / compare match flag A
;TIER-Register
OVIE equ 2 ; Overflow interrupt enable
IMIEB equ 1 ; Input capture / compare match interrupt enable B
IMIEA equ 0 ; Input capture / compare match interrupt enable A
;-----------------------------------------------------------------------------
;Programmable Timing Pattern Controller (Sec.11 p.381-406)
TPMR equ $ffa0 ; TPC output mode register
TPCR equ $ffa1 ; TPC output control register
NDERB equ $ffa2 ; Next data enable register B
NDERA equ $ffa3 ; Next data enable register A
NDRA equ $ffa5 ; Next data register A
NDRB equ $ffa4 ; Next data register B
NDRA1 equ $ffa5 ; Next data register A group 1
NDRA0 equ $ffa7 ; Next data register A group 0
NDRB3 equ $ffa4 ; Next data register B group 3
NDRB2 equ $ffa6 ; Next data register B group 2
;-----------------------------------------------------------------------------
; Watchdog: (Sec.12 p.407-422)
WDT_TCSR equ $ffa8 ; Timer control/status register
WDT_TCNT equ $ffa9 ; Timer counter
WDT_RSTCSR equ $ffab ; Reset control/status register
WDT_RSTCSRW equ $ffaa ; dito, zum setzen wordzugriffe (p.415)
;TCSR-Register
WDT_OVF equ 7 ; Overflow Flag
WDT_WTIT equ 6 ; Timer mode select
WDT_TME equ 5 ; Timer enable
WDT_CKS2 equ 2 ; Clock select
WDT_CKS1 equ 1
WDT_CKS0 equ 0
;RSTCSR-Register
WDT_WRST equ 7 ; Watchdog timer reset
WDT_RSTOE equ 6 ; Reset output enable
;-----------------------------------------------------------------------------
; serielle Schnittstelle: (Sec.13 p.423-482)
__defSCI macro Base,Name
SMR{Name} equ Base ; Serial mode register
BRR{Name} equ Base+1 ; Bit rate register
SCR{Name} equ Base+2 ; Serial control register
TDR{Name} equ Base+3 ; Transmit data register
SSR{Name} equ Base+4 ; Serial status register
RDR{Name} equ Base+5 ; Receive data register
endm
__defSCI $ffb0,"0"
__defSCI $ffb8,"1"
;SMR-Register
CA equ 7 ; Communication mode
CHR equ 6 ; Character length
PE equ 5 ; Parity enable
OE equ 4 ; Parity mode
STOP equ 3 ; Stop bit length
MP equ 2 ; Multiprocessor mode
CKS1 equ 1 ; Clock select 1
CKS0 equ 0
;SCR-Register
TIE equ 7 ; Transmit interrupt enable
RIE equ 6 ; Receive " "
TE equ 5 ; Transmit enable
RE equ 4 ; Receive enable
MPIE equ 3 ; Multiprozessor interrupt enable
TEIE equ 2 ; Transmit-end interrupt enable
CKE1 equ 1 ; Clock enable 1
CKE0 equ 0 ;
;SSR-Register
TDRE equ 7 ; Transmit data register empty
RDRF equ 6 ; Receive data register full
ORER equ 5 ; Overrun error
FER equ 4 ; Framing error
PER equ 3 ; Parity error
TEND equ 2 ; Transmit end
MPB equ 1 ; Multiprocessor bit
MPBT equ 0 ; Multiprocessor bit transfer
;-----------------------------------------------------------------------------
;Smart Card interface
;not implemented yet
;-----------------------------------------------------------------------------
; A/D-Wandler: (Sec.15 p.505-526)
ADDRA equ $ffe0
ADDRAH equ $ffe0 ;
ADDRAL equ $ffe1 ;
ADDRB equ $ffe2
ADDRBH equ $ffe2
ADDRBL equ $ffe3
ADDRC equ $ffe4
ADDRCH equ $ffe4
ADDRCL equ $ffe5
ADDRD equ $ffe6
ADDRDH equ $ffe6
ADDRDL equ $ffe7
ADCSR equ $ffe8 ; Steuer/Statusregister:
ADF equ 7 ; Wandlung abgeschlossen
ADIE equ 6 ; Interrupt bei Wandelende?
ADST equ 5 ; Wandlung starten
SCAN equ 4 ; Scan-Modus
CKS equ 3 ; Wandlungszeit
CH2 equ 2 ; Kanalauswahl
CH1 equ 1
CH0 equ 0
ADCR equ $ffe9 ; A/D control register
TRGE equ 7 ; Trigger enable
;-----------------------------------------------------------------------------
;D/A-Wandler (Sec.16 p.527-533)
DADR0 equ $ffdc ; D/A data register 0
DADR1 equ $ffdd ; D/A data register 1
DACR equ $ffde ; D/A control register
DASTCR equ $ff5c ; D/A standby control register
;DACR-Register
DAOE1 equ 7 ; D/A output enable
DAOE0 equ 6
DAE equ 5 ; D/A enable
;DASTCR-Register
DASTE equ 0 ; D/A standby enable
;-----------------------------------------------------------------------------
;Clock-Pulse Generator (Sec.19 p.607-614)
DIVCR equ $ff5d ; Divison control register
DIV1 equ 1
DIV0 equ 0
;-----------------------------------------------------------------------------
;-----------------------------------------------------------------------------
endif
restore
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