📄 h8_3048.inc
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save
listing off
; kein Listing 乥er diesen File
;****************************************************************************
;* *
;* AS 1.41 - Datei REG3048.INC *
;* *
;* Sinn : enth刲t SFR-, Makro- und Adreadefinitionen f乺 H8/3048 *
;* *
;* letzte 巒derungen : 24.10.1995 *
;* *
;****************************************************************************
ifndef reg3048inc ; verhindert Mehrfacheinbindung
reg532inc equ 1
if (MOMCPUNAME<>"HD6413309")&&(MOMCPUNAME<>"H8/300H")
fatal "Falscher Prozessortyp eingestellt: nur H8/300H erlaubt!"
endif
if MOMPASS=1
message "H8/3048-SFR-Definitionen, (C) 1995 Christian Stelter"
endif
;-----------------------------------------------------------------------------
; MCU-Operating-Modes: (Sec.3 p.55-68 & Sec.20 p.615-628)
MDCR equ $fff1 ; Arbeitsmodus CPU
SYSCR equ $fff2 ; Standby-Modusregister
MSTCR equ $ff5e ; Module standby control register
;MDCR-Register
MD0 equ 0
MD1 equ 1
MD2 equ 2
;SYSCR-Register
SSBY equ 7 ; Software-Standby
STS2 equ 6 ; Standby-Timer Select
STS1 equ 5
STS0 equ 4
UE equ 3 ; User bit enable
NMIEG equ 2 ; NMI-edge
RAME equ 0 ; internes RAM freigeben
;MSTCR-Register
PSTOP equ 7 ; Phi-clock stop
MSTOP5 equ 5 ; Module standby
MSTOP4 equ 4
MSTOP3 equ 3
MSTOP2 equ 2
MSTOP1 equ 1
MSTOP0 equ 0
;-----------------------------------------------------------------------------
; Bus-Controller (Sec.6 p.107-142)
ABWCR equ $ffec ; Bus width control register
ASTCR equ $ffed ; Access state control register
WCR equ $ffee ; Wait control register
WMS0 equ 2 ; Modus
WMS1 equ 3
WC0 equ 0 ; Anzahl Waitstates
WC1 equ 1
WCER equ $ffef ; Wait state controller enable reg.
BRCR equ $fff3 ; Bus release control register
A23E equ 7 ; Address 23 enable
A22E equ 6 ; 22
A21E equ 5 ; 21
BRLE equ 0 ; Bus release enable
CSCR equ $ff5f ; Chip select control register
CS7E equ 7 ; Chip-select 7 enabel
CS6E equ 6
CS5E equ 5
CS4E equ 4
;-----------------------------------------------------------------------------
; Interrupt-Controller:
ISCR equ $fff4 ; IRQ sense control register
IER equ $fff5 ; IRQ enable register
ISR equ $fff6 ; IRQ status register
IPRA equ $fff8 ; Priorit則ssteuerung
IPRB equ $fff9 ;
;-----------------------------------------------------------------------------
; Lage Exception und Interrupt-Vektoren: (Sec.4 p.69-78)
;
__defvec macro Name,Num
Name equ Num<<2
endm
__defvec Reset,0
__defvec NMI,7
__defvec TRAP0,8
__defvec TRAP1,9
__defvec TRAP2,10
__defvec TRAP3,11
__defvec IRQ0,12
__defvec IRQ1,13
__defvec IRQ2,14
__defvec IRQ3,15
__defvec IRQ4,16
__defvec IRQ5,17
__defvec WOVI,20
__defvec CMI,21
__defvec IMIA0,24
__defvec IMIB0,25
__defvec OVI0,26
__defvec IMIA1,28
__defvec IMIB1,29
__defvec OVI1,30
__defvec IMIA2,32
__defvec IMIB2,33
__defvec OVI2,34
__defvec IMIA3,36
__defvec IMIB3,37
__defvec OVI3,38
__defvec IMIA4,40
__defvec IMIB4,41
__defvec OVI4,42
__defvec DEND0A,44
;__defvec DEND0A,45
__defvec DEND1B,46
;__defvec DEND1B,47
__defvec ERI0,52
__defvec RXI0,53
__defvec TXI0,54
__defvec TEI0,55
__defvec ERI1,56
__defvec RXI1,57
__defvec TXI1,58
__defvec TEI1,59
__defvec ADI,60
;-----------------------------------------------------------------------------
; DMA-Controller (Sec.6 p.181-238)
DTEA equ $fff4 ; Freigabe Datentransfers
DTEB equ $fff5
DTEC equ $fff6
DTED equ $fff7
__defdma macro Base,Name
MAR{Name}AR equ Base ; Memory address register AR
MAR{Name}ER equ Base+1 ; Memory address register AE
MAR{Name}AL equ Base+2 ; Memory address register AL
MAR{Name}AH equ Base+3 ; Memory address register AH
ETCR{Name}AH equ Base+4 ; Execute transfer count register AH
ETCR{Name}AL equ Base+5 ; AL
IOAR{Name}A equ Base+6 ; I/O address register A
DTCR{Name}A equ Base+7 ; Data transfer control register A
MAR{Name}BR equ Base+8 ; Memory address register BR
MAR{Name}BE equ Base+9 ; Memory address register BE
MAR{Name}BH equ Base+10 ; Memory address register BH
MAR{Name}BL equ Base+11 ; Memory address register BL
ETCR{Name}BH equ Base+12 ; Excute transfer count register BH
ETCR{Name}BL equ Base+13 ; Excute transfer count register BL
IOAR{Name}B equ Base+14 ; I/O address register B
DTCR{Name}B equ Base+15 ; Data transfer control register
endm
__defdma $ff20,"0"
__defdma $ff30,"1"
; DTCR-Register
; short address-mode
DTE equ 7 ; Data transfer enable
DTSZ equ 6 ; Data transfer size
DTID equ 5 ; Data transfer inc/dec
RPE equ 4 ; Repeat enable
DTIE equ 3 ; Data transfer interrupt enable
DTS2 equ 2 ; Data transfer select
DTS1 equ 1
DTS0 equ 0
; full address mode
SAID equ 5 ; Source address inc/dec
SAIE equ 4 ; Source address inc/dec enable
DTS2A equ 2 ; Data transfer select
DTS1A equ 1
DTS0A equ 0
; DTCRB-Register
DTME equ 7 ; Data transfer master enable
DAID equ 5 ; Destination address inc/dec bit
DAIE equ 4 ; enable
TMS equ 3 ; Transfer mode select
DTS2B equ 2 ; Data transfer select
DTS1B equ 1
DTS0B equ 0
;-----------------------------------------------------------------------------
; I/O-Ports: (Sec.9 p.239-280)
P1DDR equ $ffc0 ; Datenrichtung Port 1
P1DR equ $ffc2 ; Daten Port 1
P2DDR equ $ffc1 ; Datenrichtung Port 2
P2DR equ $ffc3 ; Daten Port 2
P2PCR equ $ffd8 ; Input pull-up control register port 3
P3DDR equ $ffc4 ; Datenrichtung Port 3
P3DR equ $ffc6 ; Daten Port 3
P4DDR equ $ffc5 ; Datenrichtung Port 4
P4DR equ $ffc7 ; Daten Port 4
P4PCR equ $ffda ; Input pull-up control register port 4
P5DDR equ $ffc8 ; Datenrichtung Port 5
P5DR equ $ffca ; Daten Port 5
P5PCR equ $ffcb ; Input pull-up control register port 5
P6DDR equ $ffc9 ; Datenrichtung Port 6
P6DR equ $ffcb ; Daten Port 6
P8DDR equ $ffcd ; Datenrichtung Port 8
P8DR equ $ffcf ; Daten Port 8
P9DDR equ $ffd0 ; Datenrichtung Port 9
P9DR equ $ffd2 ; Daten Port 9
PADDR equ $ffd1 ; Datenrichtung Port A
PADR equ $ffd3 ; Daten Port A
PBDDR equ $ffd4 ; Datenrichtung Port B
PBDR equ $ffd6 ; Daten Port B
;------------------------------------------------------------------------------
;Integrated Timer Unit (ITU): (Sec.10 p.281-380)
;common
TSTR equ $ff60 ; Timer start register
TSNC equ $ff61 ; Timer synchro register
TMDR equ $ff62 ; Timer mode register
TFCR equ $ff63 ; Timer function control register
TOER equ $ff90 ; Timer output master enable register
TOCR equ $ff91 ; Timer output control register
__deftimer macro Base,Name
TCR{Name} equ Base ; Timer control register
TIOR{Name} equ Base+1 ; Timer I/O control register
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