📄 gpiflongxfr.lst
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C51 COMPILER V6.10 GPIFLONGXFR 07/07/2005 13:31:08 PAGE 1
C51 COMPILER V6.10, COMPILATION OF MODULE GPIFLONGXFR
OBJECT MODULE PLACED IN .\gpiflongxfr.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE .\gpiflongxfr.c OPTIMIZE(6,SPEED) D
-EBUG OBJECTEXTEND CODE SYMBOLS PAGEWIDTH(80)
stmt level source
1 #pragma NOIV // Do not generate interrupt vecto
-rs
2 //----------------------------------------------------------------
--------------
3 // File: gpiflongxfr.c
4 //
5 // Contents: Hooks required to implement USB peripheral functio
-n.
6 // Code written for EZUSB FX2 128-pin REVE...
7 // Firmware tested on EZUSB FX2 128-pin (CY3681 DK)
8 // Copyright (c) 2001 Cypress Semiconductor All rights reserved
9 //----------------------------------------------------------------
--------------
10 #include "fx2.h"
11 #include "fx2regs.h"
12 #include "fx2sdly.h" // SYNCDELAY macro
13
14 extern BOOL GotSUD; // Received setup data flag
15 extern BOOL Sleep;
16 extern BOOL Rwuen;
17 extern BOOL Selfpwr;
18
19 BYTE Configuration; // Current configuration
20 BYTE AlternateSetting; // Alternate settings
21
22
23 BOOL xfrvia_TD_Poll = 0; // Event flg for execution in TD_Poll(
- );
24 BOOL in_token_event = 0; // Event flg for GPIF FIFO Read trigge
-r
25
26
27
28
29 // proto's from "gpif.c"
30 void GpifInit( void );
31
32
33 // it may be worth noting here that the default monitor loads at
- 0xC000
34
35 // use this global variable when (de)asserting debug LEDs...
36
37 // 512 for high speed, 64 for full speed
38 static WORD enum_pkt_size = 0x0000;
39
40 // when set firmware running in TD_Poll( ); handles data transfers
41 BOOL td_poll_handles_transfers = 0;
42
43 // when set cpu is out of the data path
44 BOOL endp_auto_mode_enabled = 0;
45
46 //////////////////////////////////////////////////////////////////
-///////
C51 COMPILER V6.10 GPIFLONGXFR 07/07/2005 13:31:08 PAGE 2
47 #define VX_A2 0xA2 // testing, GPIF single byte read waveform
48 #define VX_A3 0xA3 // testing, GPIF single byte write waveform
49 #define VX_A7 0xA7 // setup peripheral for high speed FIFO xfr(
-s), TC=8
50 #define VX_A8 0xA8 // do a FIFO Rd transaction w/TC=8 into EP8
51 #define VX_AC 0xAC // manually commit IN data to host... INPKTE
-ND
52
53 #define VX_C5 0xC5 // for test purpose
54
55 #define VX_D0 0xD0 // read GPIFTCx registers
56 #define VX_D1 0xD1 // let TD_Poll( ); firmware handle data xfr'
-s...
57 #define VX_D2 0xD2 // handle data xfr's via vendor specific cmd
-s...
58
59 #define VX_EE 0xEE //reset address bus
60
61 /////////////////////////////////////////fiber manufaction command
- //////
62 #define VX_E0 0xE0 //握手
63 #define VX_E1 0xE1 //电子开关
64 #define VX_E2 0xE2 //电机行进
65 #define VX_E3 0xE3 //长周期光栅
66 #define VX_E4 0xE4 //电子开关,按存储器中延时数据制作布拉格光栅
67 #define VX_E5 0xE5 //数据传输初始化
68 //////////////////////////////////////////////////////////////////
-////////
69 //////////////////////////////////////define port
70 sbit O_STEP = IOA ^ 0;//PA.0电机步进脉冲
71 sbit O_DIR = IOA ^ 1;//PA.1电机方向
72 sbit O_ENABLE = IOA ^ 2;//PA.2电机使能(高->允许,低->禁止)
73 sbit O_SWITCH = IOA ^ 3;//PA.3电子开关(高->关闭,低->打开)
74
75 //////////////////////////////////////define variable
76 static WORD HighAddr;//高位地址
77 BYTE R_SPEED;//延时的机器周期数
78 BYTE R_STEP1;//电机行进步数高8位
79 BYTE R_STEP2;//电机行进步数250对应5um
80 BYTE R_STEP3;//电机行进步数200对应200*5um=1mm
81 BYTE R_LENGTH;//光栅长度,为光栅周期倍数
82 BYTE R_TIME1;//曝光时间高8位
83 BYTE R_TIME2;//曝光时间低8位
84 BYTE R_COEF;//写BRAG光栅时的倍数
85 BYTE R_SETTING;//命令
86 BOOL S_SWITCH;//电子开关设定
87 ////////////////////////////////////////////////////////
88
89 //----------------------------------------------------------------
--------------
90 // Task Dispatcher hooks
91 // The following hooks are called by the task dispatcher.
92 //----------------------------------------------------------------
--------------
93 void TD_Init( void )
94 { // Called once at startup
95 1
96 1
97 1 CPUCS = 0x02; // CLKSPD[1:0]=10, for 48MHz opera
-tion///10
98 1 // CPUCS = 0x12; // CLKOE=0, don't d
-rive CLKOUT
C51 COMPILER V6.10 GPIFLONGXFR 07/07/2005 13:31:08 PAGE 3
99 1
100 1 GpifInit( ); // init GPIF engine via GPIFTool o
-utput file
101 1
102 1 SYNCDELAY; // see TRM section 15.14
103 1 REVCTL = 0x02; // REVCTL.1=1; use "dynamic OUT au
-tomaticity"
104 1
105 1 // EP2 512 BULK OUT 4x
106 1 SYNCDELAY; // see TRM section 15.14
107 1 EP2CFG = 0xA0; // BUF[1:0]=00 for 4x buffering
108 1
109 1 // EP6 512 BULK IN 4x
110 1 SYNCDELAY; //
111 1 EP6CFG = 0xE0; // BUF[1:0]=00 for 4x buffering
112 1
113 1 // EP4 and EP8 are not used in this implementation...
114 1 SYNCDELAY; //
115 1 EP4CFG = 0x20; // clear valid bit
116 1 SYNCDELAY; //
117 1 EP8CFG = 0x60; // clear valid bit
118 1
119 1 SYNCDELAY; //
120 1 FIFORESET = 0x80; // activate NAK-ALL to avoid race
-conditions
121 1 SYNCDELAY; //
122 1 FIFORESET = 0x02; // reset, FIFO 2
123 1 SYNCDELAY; //
124 1 FIFORESET = 0x04; // reset, FIFO 4
125 1 SYNCDELAY; //
126 1 FIFORESET = 0x06; // reset, FIFO 6
127 1 SYNCDELAY; //
128 1 FIFORESET = 0x08; // reset, FIFO 8
129 1 SYNCDELAY; //
130 1 FIFORESET = 0x00; // deactivate NAK-ALL
131 1
132 1 // 8-bit bus (WORDWIDE=0)...
133 1 SYNCDELAY; //
134 1 EP2FIFOCFG = 0x00;
135 1 SYNCDELAY; //
136 1 EP6FIFOCFG = 0x04;
137 1
138 1 SYNCDELAY; //
139 1 EP2BCL = 0x80; // arm first buffer
140 1 SYNCDELAY; //
141 1 EP2BCL = 0x80; // arm second buffer
142 1 SYNCDELAY; //
143 1 EP2BCL = 0x80; // arm third buffer
144 1 SYNCDELAY; //
145 1 EP2BCL = 0x80; // arm fourth buffer
146 1 SYNCDELAY; //
147 1
148 1 // Note: had we choosen to use AUTOOUT=1 initially, then...
149 1 // (1)...when REVCTL.1=0, the core must see MANUAL-AUTO switch
- of AUTO bit
150 1 // ...to properly "arm" OUT buffers...
151 1 //
152 1 // SYNCDELAY;
153 1 // EP2FIFOCFG = 0x00; // AUTOOUT=0 (manual OUT mode)
154 1 // SYNCDELAY;
155 1 // EP6FIFOCFG = 0x04;
156 1 // then,
C51 COMPILER V6.10 GPIFLONGXFR 07/07/2005 13:31:08 PAGE 4
157 1 // SYNCDELAY;
158 1 // EP2FIFOCFG = 0x10; // AUTOOUT=1 (auto OUT mode)
159 1 // SYNCDELAY;
160 1 // EP6FIFOCFG = 0x04;
161 1 //
162 1 // ...this might not be obvious because the default is AUTO
-OUT=0
163 1 // ...power static back to back firmware downloads may be s
-ubject to
164 1 // ...the above scheme.when the application's last status w
-as AUTOOUT=1
165 1 //
166 1 // (2)...when REVCTL.1=1, core blocks auto arming of OUT endp'
-s
167 1 // ...see above EPxBCL/OUTPKTEND sequence(s)
168 1 // ...sequence is as follows:
169 1 // ...(a) REVCTL.1=1
170 1 // ...(b) FIFORESET (as above)
171 1 // ...(c) EPxBCL/OUTPKTEND (as above)
172 1 // ...(d) AUTOOUT=1
173 1
174 1
175 1 // IN endp's come up in the cpu/peripheral domain
176 1
177 1
178 1 // setup INT4 as internal source for GPIF interrupts
179 1 // using INT4CLR (SFR), automatically enabled
180 1 INTSETUP |= 0x03; // Enable INT4 FIFO/GPIF Autovectoring
181 1 SYNCDELAY; // used here as "delay"
182 1 EXIF &= ~0x40; // just in case one was pending...
183 1 SYNCDELAY; // used here as "delay"
184 1 GPIFIRQ = 0x02;
185 1 SYNCDELAY; //
186 1 GPIFIE = 0x02; // Enable GPIFWF interrupt
187 1 SYNCDELAY; //
188 1 EIE |= 0x04; // Enable INT4 ISR, EIE.2(EIEX4=1)
189 1
190 1 SYNCDELAY;
191 1 GPIFIDLECTL=0xFc;
192 1 SYNCDELAY;
193 1
194 1
195 1 }
196
197 #define GPIFTRIGWR 0
198 #define GPIFTRIGRD 4
199
200 #define GPIF_EP2 0
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