📄 gpiflongxfr.c
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{
}
XGPIFSGLDATLX = 0xA3; // Trigger GPIF
*EP0BUF = 0xA3;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with # bytes to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
break;
}
case VX_A7:
{ // Setup peripheral for high speed FIFO xfr(s), TC=8 bytes
EP6GPIFTCH = 0x00; // setup transaction count
EP6GPIFTCL = 0x40; // set EP8GPIFTC = 8
*EP0BUF = 0xA7;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with # bytes to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
break;
}
case VX_A8:
{ // Do a FIFO Rd transaction w/TC=8 into EP8
if( !( EP2468STAT & 0x20 ) )
{ // EP8FF=0, when buffer is available...
// trigger FIFO read transaction(s), using SFR
while( !( GPIFTRIG & 0x80 ) ) // Poll GPIFTRIG.7 Done bit
{
}
GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)
*EP0BUF = 0xA8; // return that there was a buffer available
}
else
{ // If EP busy then host is behind...
*EP0BUF = 0x00; // Buffer space wasn't available and we still have
// two buffers containing data
}
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with # bytes to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
break;
}
case VX_AC:
{ // manually commit IN data to host...
// GPIF needs to still be pointing to EP8, last FIFO accessed
if( EP2468STAT & 0x20 )
{ // EP6F=1 when buffer is not available
*EP0BUF = 0x00; // buffer wasn't available
}
else
{ // EP8F=0 when buffer is available
INPKTEND = 0x06; // 8051 commits pkt by writing #8 to INPKTEND
*EP0BUF = 0xAC;
}
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with # bytes to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
break;
}
case VX_C5:
{ // read REVCTL register
HighAddr=0xAAAA;
EP0BUF[0]=LSB(HighAddr>>3);
EP0BUF[1]=MSB(HighAddr>>3);
EP0BCH = 0;
EP0BCL = 2; // Arm endpoint with # bytes to transfer
EP0CS |= bmHSNAK;
return( FALSE );
break;
}
case VX_D0:
{ // read live GPIF address
EP0BUF[0] = VX_D0;
SYNCDELAY;
EP0BUF[3]=GPIFADRH;
SYNCDELAY;
EP0BUF[4]=GPIFADRL;
EP0BUF[2]=IOD;
EP0BUF[1]=IOE;
EP0BCH = 0;
EP0BCL = 5; // Arm endpoint with # bytes to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
return( FALSE ); // no error; command handled OK
break;
}
case VX_D1:
{ // setup GPIF transaction count
xfrvia_TD_Poll = 1;
in_token_event=0;
//ledX_rdvar = LED0_ON; // LED0 is ON: GPIF triggered in TD_POll
*EP0BUF = 0xD1;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with # bytes to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
break;
}
case VX_D2:
{
xfrvia_TD_Poll = 0;
in_token_event=1;
//ledX_rdvar = LED0_OFF; // LED0 is OFF: GPIF not triggered in TD_Poll
*EP0BUF = 0xD2;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with # bytes to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
break;
}
case VX_E0://握手
{
*EP0BUF=VX_E0;
break;
}
case VX_E1://电子开关 EP0BUF[1]＝0x00关闭，EP0BUF【1】＝0x01打开
{
if(EP0BUF[1]&0x01)
IOA &=0xF7;//IOA.3=0
else
IOA |=0x08;//IOA.3=1
*EP0BUF=VX_E1;
break;
}
case VX_E2:
//电机行进,四个字节命令，EP0BUF【0】为原始命令，EP0BUF【1】存储设置信息，
//EP0BUF【2】控制电机速度（延时参数），EP0BUF【3】为行进步数
//EP0BUF【1】.0设置方向O_DIR，EP0BUF【1】。1设置电子开关O_SWITCH，SWITCH=0关闭，SWITCH＝1打开
{
R_SETTING=EP0BUF[1];
R_SPEED=EP0BUF[2];
R_STEP1=EP0BUF[3];
R_STEP2=0xFA;//=250
R_STEP3=0xC8;//=200
SUB_SETTING();
SUB_STEPIN();
*EP0BUF=VX_E2;
break;
}
case VX_E3://长周期光栅的制作
{
R_SETTING=EP0BUF[1];
R_SPEED=EP0BUF[2];
R_STEP1=EP0BUF[3];
R_STEP2=0xFA;//250
R_LENGTH=EP0BUF[4];
R_TIME1=EP0BUF[5];
R_TIME2=EP0BUF[6];
SUB_SETTING();
SUB_F1();
*EP0BUF=VX_E3;
break;
}
/* case VX_E4:
{
if( EP68FIFOFLGS & 0x01 )
{ // EP6FF=1, when fifo "full"
SYNCDELAY; //
INPKTEND = 0x06; // ...skip pkt.
}
else
{ // EP6FF=0, when fifo "not full", buffer available...
// setup GPIF transaction count
SYNCDELAY; //
EP6GPIFTCH = 0x02;
SYNCDELAY;
EP6GPIFTCL = 0x00;
// trigger FIFO read transaction(s), using SFR
// R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)
SYNCDELAY;
GPIFTRIG = GPIFTRIGRD | GPIF_EP6;
// NOTE: 512 bytes transfers in ~75usec on 8-bit async bus ;64 bytes transfers in ~10usec on 8-bit async bus
// wait for the transaction to terminate naturally...
SYNCDELAY; //
while( !( GPIFTRIG & 0x80 ) )
{ // should take <75usec @ 8-bit async.
; // poll GPIFTRIG.7, DONE bit...
}
}
*EP0BUF=VX_E4;
break;
//电子开关,按存储器数据运行
{
if(EP0BUF[1]&0x02)
{
IOA&=0xF7;//CLR O_SWTICH
}
else
{
}
IOA&=0xFD;//CLR O_DIR
R_COEF=EP0BUF[2];
ReadFlag=1;
IOD=0x00;
IOE=0x00;
AUTOPTRSETUP = 0x07;
while(ReadFlag)
{
AUTOPTRH2 = 0xF8;
AUTOPTRL2 = 0x00;//EP6BUFFER
//if ep6full is full then do work;close switch;skip packet;ep6full=0;ReadFlag=1;
// Handle IN data...
// is the peripheral interface idle...
if( GPIFTRIG & 0x80 )
{ // check if peripheral "not empty"...
if( EP68FIFOFLGS & 0x01 )
{ // EP6FF=1, when fifo "full"
BYTE i,j,k,l,delay;
for(l=2;l>0;l--)
{
for(i=256;i>0;i--)
{
IOA^=0x01;
delay=EXTAUTODAT2;
if(!delay)
{
ReadFlag=0;
IOA|=0x08;
i=0;
j=0;
}
IOA^=0x01;
for(j=R_COEF;j>0;j--)//延时
{
for(k=delay;k>0;k--);
}
}
}
IOD+=1;
if(PSW&0x80)
{
IOE+=1;
}
SYNCDELAY; //
INPKTEND = 0x16; // ...skip pkt.
}
else
{ // EP6FF=0, when fifo "not full", buffer available...
// setup GPIF transaction count
SYNCDELAY; //
EP6GPIFTCH = 0x02;
SYNCDELAY;
EP6GPIFTCL = 0x00;
// trigger FIFO read transaction(s), using SFR
// R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)
SYNCDELAY;
GPIFTRIG = GPIFTRIGRD | GPIF_EP6;
// NOTE: 512 bytes transfers in ~75usec on 8-bit async bus ;64 bytes transfers in ~10usec on 8-bit async bus
// wait for the transaction to terminate naturally...
SYNCDELAY; //
while( !( GPIFTRIG & 0x80 ) )
{ // should take <75usec @ 8-bit async.
; // poll GPIFTRIG.7, DONE bit...
}
}
}
else
{ // peripheral interface busy...
}
}
IOA|=0x08;
*EP0BUF=VX_E4;
break;
}
*/ case VX_E5:
//数据传输的初始化工作
{
IOD=0x00;
IOE=0x00;
*EP0BUF=VX_E5;
break;
}
case VX_EE:
{
// GPIF address pins update when GPIFADRH/L written
SYNCDELAY; //
GPIFADRH = 0x00; // bits[7:1] always 0
SYNCDELAY; //
GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
IOD=0x00;
IOE=0x00;
HighAddr=0x0000;
*EP0BUF = 0xEE;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with # bytes to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
break;
}
////////////////////////////////////////////////////////////////////////////////////////////
default:
{
//ledX_rdvar = LED3_ON; // debug visual, stuck "ON" to warn developer...
return( FALSE ); // no error; command handled OK
}
}
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with # bytes to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
return( FALSE ); // no error; command handled OK
}
//-----------------------------------------------------------------------------
// USB Interrupt Handlers
// The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------
// Setup Data Available Interrupt Handler
void ISR_Sudav( void ) interrupt 0
{
GotSUD = TRUE; // Set flag
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSUDAV; // Clear SUDAV IRQ
}
// Setup Token Interrupt Handler
void ISR_Sutok( void ) interrupt 0
{
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSUTOK; // Clear SUTOK IRQ
}
void ISR_Sof( void ) interrupt 0
{
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSOF; // Clear SOF IRQ
}
void ISR_Ures( void ) interrupt 0
{
if ( EZUSB_HIGHSPEED( ) )
{
pConfigDscr = pHighSpeedConfigDscr;
pOtherConfigDscr = pFullSpeedConfigDscr;
}
else
{
pConfigDscr = pFullSpeedConfigDscr;
pOtherConfigDscr = pHighSpeedConfigDscr;
}
EZUSB_IRQ_CLEAR( );
USBIRQ = bmURES; // Clear URES IRQ
}
void ISR_Susp( void ) interrupt 0
{
Sleep = TRUE;
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSUSP;
}
void ISR_Highspeed( void ) interrupt 0
{
if ( EZUSB_HIGHSPEED( ) )
{
pConfigDscr = pHighSpeedConfigDscr;
pOtherConfigDscr = pFullSpeedConfigDscr;
}
else
{
pConfigDscr = pFullSpeedConfigDscr;
pOtherConfigDscr = pHighSpeedConfigDscr;
}
EZUSB_IRQ_CLEAR( );
USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack( void ) interrupt 0
{
}
void ISR_Stub( void ) interrupt 0
{
}
void ISR_Ep0in( void ) interrupt 0
{
}
void ISR_Ep0out( void ) interrupt 0
{
}
void ISR_Ep1in( void ) interrupt 0
{
}
void ISR_Ep1out( void ) interrupt 0
{
}
void ISR_Ep2inout( void ) interrupt 0
{
}
void ISR_Ep4inout( void ) interrupt 0
{
}
void ISR_Ep6inout( void ) interrupt 0
{
}
void ISR_Ep8inout( void ) interrupt 0
{
}
void ISR_Ibn( void ) interrupt 0
{
}
void ISR_Ep0pingnak( void ) interrupt 0
{
}
void ISR_Ep1pingnak( void ) interrupt 0
{
}
void ISR_Ep2pingnak( void ) interrupt 0
{
}
void ISR_Ep4pingnak( void ) interrupt 0
{
}
void ISR_Ep6pingnak( void ) interrupt 0
{
}
void ISR_Ep8pingnak( void ) interrupt 0
{
}
void ISR_Errorlimit( void ) interrupt 0
{
}
void ISR_Ep2piderror( void ) interrupt 0
{
}
void ISR_Ep4piderror( void ) interrupt 0
{
}
void ISR_Ep6piderror( void ) interrupt 0
{
}
void ISR_Ep8piderror( void ) interrupt 0
{
}
void ISR_Ep2pflag( void ) interrupt 0
{
}
void ISR_Ep4pflag( void ) interrupt 0
{
}
void ISR_Ep6pflag( void ) interrupt 0
{
}
void ISR_Ep8pflag( void ) interrupt 0
{
}
void ISR_Ep2eflag( void ) interrupt 0
{
}
void ISR_Ep4eflag( void ) interrupt 0
{
}
void ISR_Ep6eflag( void ) interrupt 0
{
}
void ISR_Ep8eflag( void ) interrupt 0
{
}
void ISR_Ep2fflag( void ) interrupt 0
{
}
void ISR_Ep4fflag( void ) interrupt 0
{
}
void ISR_Ep6fflag( void ) interrupt 0
{
}
void ISR_Ep8fflag( void ) interrupt 0
{
}
void ISR_GpifComplete( void ) interrupt 0
{
}
void ISR_GpifWaveform( void ) interrupt 0
{ // FIFORd WF detected peripheral prematurely empty (less than max. pkt. size)
GPIFABORT = 0xFF; // abort to handle shortpkt
SYNCDELAY;
EXIF &= ~0x40;
INT4CLR = 0xFF; // automatically enabled at POR
SYNCDELAY;
}
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