cachelib.c

VxWorks操作系统内核源代码

    CACHE_TYPE	cache,		/* cache to lock */
    void *	address,	/* virtual address */
    size_t	bytes		/* number of bytes to lock */
    )
    {
    return ((cacheLib.lockRtn == NULL) ? ERROR : 
            (cacheLib.lockRtn) (cache, address, bytes));
    }

/**************************************************************************
*
* cacheUnlock - unlock all or part of a specified cache
*
* This routine unlocks all (global) or some (local) entries in the 
* specified cache.  Not all caches can perform unlocking.
*
* RETURNS: OK, or ERROR if the cache type is invalid or the cache control
* is not supported.
*/

STATUS cacheUnlock
    (
    CACHE_TYPE	cache,		/* cache to unlock */
    void *	address,	/* virtual address */
    size_t	bytes		/* number of bytes to unlock */
    )
    {
    return ((cacheLib.unlockRtn == NULL) ? ERROR : 
            (cacheLib.unlockRtn) (cache, address, bytes));
    }

/**************************************************************************
*
* cacheFlush - flush all or some of a specified cache
*
* This routine flushes (writes to memory) all or some of the entries in
* the specified cache.  Depending on the cache design, this operation may
* also invalidate the cache tags.  For write-through caches, no work needs
* to be done since RAM already matches the cached entries.  Note that
* write buffers on the chip may need to be flushed to complete the flush.
*
* RETURNS: OK, or ERROR if the cache type is invalid or the cache control
* is not supported.
*/

STATUS cacheFlush
    (
    CACHE_TYPE	cache,		/* cache to flush */
    void *	address,	/* virtual address */
    size_t	bytes		/* number of bytes to flush */
    )
    {
    return ((cacheLib.flushRtn == NULL) ? OK : 
            (cacheLib.flushRtn) (cache, address, bytes));
    }

/**************************************************************************
*
* cacheInvalidate - invalidate all or some of a specified cache
*
* This routine invalidates all or some of the entries in the
* specified cache.  Depending on the cache design, the invalidation
* may be similar to the flush, or one may invalidate the tags directly.
*
* RETURNS: OK, or ERROR if the cache type is invalid or the cache control
* is not supported.
*/

STATUS cacheInvalidate
    (
    CACHE_TYPE	cache,		/* cache to invalidate */
    void *	address,	/* virtual address */
    size_t	bytes		/* number of bytes to invalidate */
    )
    {
    return ((cacheLib.invalidateRtn == NULL) ? OK : 
            (cacheLib.invalidateRtn) (cache, address, bytes));
    }

/**************************************************************************
*
* cacheClear - clear all or some entries from a cache
*
* This routine flushes and invalidates all or some entries in the
* specified cache.
*
* RETURNS: OK, or ERROR if the cache type is invalid or the cache control
* is not supported.
*/

STATUS cacheClear
    (
    CACHE_TYPE	cache,		/* cache to clear */
    void *	address,	/* virtual address */
    size_t	bytes		/* number of bytes to clear */
    )
    {
    return ((cacheLib.clearRtn == NULL) ? ERROR : 
            (cacheLib.clearRtn) (cache, address, bytes));
    }

/**************************************************************************
*
* cachePipeFlush - flush processor write buffers to memory
*
* This routine forces the processor output buffers to write their contents 
* to RAM.  A cache flush may have forced its data into the write buffers, 
* then the buffers need to be flushed to RAM to maintain coherency.
*
* RETURNS: OK, or ERROR if the cache control is not supported.
*/

STATUS cachePipeFlush (void)
    {
    return ((cacheLib.pipeFlushRtn == NULL) ? OK :
            (cacheLib.pipeFlushRtn) ());
    }

/**************************************************************************
*
* cacheTextUpdate - synchronize the instruction and data caches
*
* This routine flushes the data cache, then invalidates the instruction 
* cache.  This operation forces the instruction cache to fetch code that 
* may have been created via the data path.
*
* RETURNS: OK, or ERROR if the cache control is not supported.
*/

STATUS cacheTextUpdate 
    (
    void * address,		/* virtual address */
    size_t bytes		/* number of bytes to sync */
    )
    {
    /* if address not valid, return */
    if ((UINT32) address == NONE)
	return ERROR;

    return ((cacheLib.textUpdateRtn == NULL) ? OK :
            (cacheLib.textUpdateRtn) (address, bytes));
    }

/**************************************************************************
*
* cacheDmaMalloc - allocate a cache-safe buffer for DMA devices and drivers
*
* This routine returns a pointer to a section of memory that will not 
* experience any cache coherency problems.  Function pointers in the 
* CACHE_FUNCS structure provide access to DMA support routines.
*
* RETURNS: A pointer to the cache-safe buffer, or NULL.
*/

void * cacheDmaMalloc 
    (
    size_t bytes		/* number of bytes to allocate */
    )
    {
    return ((cacheDmaMallocRtn == NULL) ?
	    malloc (bytes) : ((void *) (cacheDmaMallocRtn) (bytes)));
    }

/**************************************************************************
*
* cacheDmaFree - free the buffer acquired with cacheDmaMalloc()
*
* This routine frees the buffer returned by cacheDmaMalloc().
*
* RETURNS: OK, or ERROR if the cache control is not supported.
*/

STATUS cacheDmaFree 
    (
    void * pBuf			/* pointer to malloc/free buffer */
    )
    {
    return ((cacheDmaFreeRtn == NULL) ?
	    free (pBuf), OK : (cacheDmaFreeRtn) (pBuf));
    }

/**************************************************************************
*
* cacheFuncsSet - set cache functions according to configuration
*
* This routine initializes the various CACHE_FUNCS structures.
*
* NOMANUAL
*/

void cacheFuncsSet (void)
    {
    if ((cacheDataEnabled == FALSE) || 
	(cacheDataMode & CACHE_SNOOP_ENABLE))
	{
	/* no cache or fully coherent cache */

	cacheUserFuncs = cacheNullFuncs;
	cacheDmaFuncs  = cacheNullFuncs;

#if	(CPU == MC68060)
	cacheDmaMallocRtn = cacheLib.dmaMallocRtn;
	cacheDmaFreeRtn	  = cacheLib.dmaFreeRtn;;
#else
	cacheDmaMallocRtn = NULL;
	cacheDmaFreeRtn	  = NULL;
#endif	/* (CPU == MC68060) */
	}
    else
	{
	/* cache is not fully coherent */

	cacheUserFuncs.invalidateRtn = cacheLib.invalidateRtn;

	if (cacheDataMode & CACHE_WRITETHROUGH)
	    cacheUserFuncs.flushRtn = NULL;
	else
	    cacheUserFuncs.flushRtn = cacheLib.flushRtn;

#if	(CPU_FAMILY==I80X86)	/* for write-back external cache */
	cacheUserFuncs.flushRtn = cacheLib.flushRtn;
#endif


	if (cacheMmuAvailable)
	    {
	    /* MMU available - dma buffers will be made non-cacheable */

	    cacheDmaFuncs.flushRtn	= NULL;
	    cacheDmaFuncs.invalidateRtn	= NULL;
	    cacheDmaFuncs.virtToPhysRtn	= cacheLib.dmaVirtToPhysRtn;
	    cacheDmaFuncs.physToVirtRtn	= cacheLib.dmaPhysToVirtRtn;

	    cacheDmaMallocRtn		= cacheLib.dmaMallocRtn;
	    cacheDmaFreeRtn		= cacheLib.dmaFreeRtn;
	    }
	else
	    {
	    /* no MMU - dma buffers are same as regular buffers */

	    cacheDmaFuncs = cacheUserFuncs;

	    cacheDmaMallocRtn = NULL;
	    cacheDmaFreeRtn   = NULL;
	    }
	}
    }

/**************************************************************************
* 
* cacheDrvFlush - flush the data cache for drivers
*
* This routine flushes the data cache entries using the function pointer 
* from the specified set.
* 
* RETURNS: OK, or ERROR if the cache control is not supported.
*/

STATUS cacheDrvFlush 
    (
    CACHE_FUNCS * pFuncs,	/* pointer to CACHE_FUNCS */
    void * address,		/* virtual address */
    size_t bytes		/* number of bytes to flush */
    )
    {
    return (CACHE_DRV_FLUSH (pFuncs, address, bytes));
    }

/**************************************************************************
* 
* cacheDrvInvalidate - invalidate data cache for drivers
* 
* This routine invalidates the data cache entries using the function pointer 
* from the specified set.
*
* RETURNS: OK, or ERROR if the cache control is not supported.
*/

STATUS cacheDrvInvalidate 
    (
    CACHE_FUNCS * pFuncs,	/* pointer to CACHE_FUNCS */
    void * address,		/* virtual address */
    size_t bytes		/* no. of bytes to invalidate */
    )
    {
    return (CACHE_DRV_INVALIDATE (pFuncs, address, bytes));
    }

/**************************************************************************
* 
* cacheDrvVirtToPhys - translate a virtual address for drivers
* 
* This routine performs a virtual-to-physical address translation using the 
* function pointer from the specified set.
* 
* RETURNS: The physical address translation of a virtual address argument.
*/

void * cacheDrvVirtToPhys 
    (
    CACHE_FUNCS * pFuncs,	/* pointer to CACHE_FUNCS */
    void * address		/* virtual address */
    )
    {
    return (CACHE_DRV_VIRT_TO_PHYS (pFuncs, address));
    }

/**************************************************************************
* 
* cacheDrvPhysToVirt - translate a physical address for drivers
* 
* This routine performs a physical-to-virtual address translation using the 
* function pointer from the specified set.
* 
* RETURNS: The virtual address that maps to the physical address argument.
*/

void * cacheDrvPhysToVirt 
    (
    CACHE_FUNCS * pFuncs,	/* pointer to CACHE_FUNCS */
    void * address		/* physical address */
    )
    {
    return (CACHE_DRV_PHYS_TO_VIRT (pFuncs, address));
    }