dsp280x_epwm.c

SVPWM算法的DSP源码已通过硬件验证

//---------------------------------------------------------------------------
// Example: InitTzGpio: 
//---------------------------------------------------------------------------
// This function initializes GPIO pins to function as Trip Zone (TZ) pins
//
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
// peripheral functional pins. By default all pins come up as GPIO
// inputs after reset.  
// 

void InitTzGpio(void)
{
   EALLOW;
   
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user. 
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
   GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0;    // Enable pull-up on GPIO12 (TZ1)
   GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0;    // Enable pull-up on GPIO13 (TZ2)
   GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0;    // Enable pull-up on GPIO14 (TZ3)
   GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0;    // Enable pull-up on GPIO15 (TZ4)

   GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0;    // Enable pull-up on GPIO16 (TZ5)
// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0;    // Enable pull-up on GPIO28 (TZ5)

   GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0;    // Enable pull-up on GPIO17 (TZ6) 
// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0;    // Enable pull-up on GPIO29 (TZ6)  
   
/* Set qualification for selected pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.  
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.

   GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3;  // Asynch input GPIO12 (TZ1)
   GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3;  // Asynch input GPIO13 (TZ2)
   GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3;  // Asynch input GPIO14 (TZ3)
   GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3;  // Asynch input GPIO15 (TZ4)

   GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3;  // Asynch input GPIO16 (TZ5)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3;  // Asynch input GPIO28 (TZ5)

   GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3;  // Asynch input GPIO17 (TZ6) 
// GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3;  // Asynch input GPIO29 (TZ6)  

   
/* Configure TZ pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be TZ functional pins.
// Comment out other unwanted lines.   
   GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1;  // Configure GPIO12 as TZ1
   GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1;  // Configure GPIO13 as TZ2
   GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1;  // Configure GPIO14 as TZ3
   GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1;  // Configure GPIO15 as TZ4

   GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3;  // Configure GPIO16 as TZ5
// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3;  // Configure GPIO28 as TZ5

   GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3;  // Configure GPIO17 as TZ6               
// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3;  // Configure GPIO29 as TZ6  

   EDIS;
}

void InitEPwm1Example()
{

 


	EPwm1Regs.TBPHS.half.TBPHS = 0;

	EPwm1Regs.TBCTL.all = 0x0012;
  	/*
	bit	15-14	00:		FREE,SOFT
	bit	13		0:  	PHSDIR
	bit	12-10	000:	CLKDIV
	bit	9-7		000:	HSPCLKDIV
	bit	6		0:		SWFSYNC
	bit 5-4		01:		SYNCOSEL	tb_ctr_zero
	bit 3		0:		PRDLD		loaded from shadow register
	bit 2		0:		PHSEN		disable
	bit 1-0		10:		CTRMODE		up and down
	*/
	//EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
	//EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
 	//EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
 	//EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	//EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1 ;
	//EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

	EPwm1Regs.AQCSFRC.all = 0x5;	// Force a continuous low on output EPWM1A and EPWM1B

	EPwm1Regs.AQCTLA.all = 0x0090;
	// bit 7-6		01:		CAD		force EPWMxA output low when counter decrements to CMPA
	// bit 5-4		10:		CAU		force EPWMxA output high when counter increments to CMPA


	EPwm1Regs.AQCTLB.all = 0x0060;
	// bit 7-6		10:		CAD		force EPWMxA output high when counter decrements to CMPA
	// bit 5-4		01:		CAU		force EPWMxA output low when counter increments to CMPA

//	EPwm1Regs.DBCTL.all = 0x000B;
	// bit 5-4: IN_MODE    00   EPWMxA is the source for the both rising-edge delay and falling-edge delay signal
	// bit 3-2: POLSEL	   10   Active low complementary mode
	// bit 1-0: OUT_MODE   11  Dead band is fully enabled for both rising-edge and falling-edge

//	EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
//	EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
//	EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
	EPwm1Regs.DBFED = 200;			// 200 * 16.67ns = 3.3us
	EPwm1Regs.DBRED = 200;			// 200 * 16.67ns = 3.3us

	EPwm1Regs.TBCTR = 0;

	EPwm1Regs.ETSEL.all = 0x0909;
	/*
	bit	15		0:		SOCBEN	enable EPWMxSOCB pulse
	bit 14-12   000:	SOCBSEL	enable event time-base counter equal to zero
	bit 11		1:		SCOAEN  enable EPWMxSOCA
	bit 10-8    001:	SOCASEL enable event time-base counter equal to zero
	bit 3		0:		INTEN	disable
	bit	2-0		001:	INTSEL	counter equal to zero
	*/
	//EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;		//epwm1_tbctr = 0 时中断
	//EPwm1Regs.ETSEL.bit.INTEN = ET_DISABLE;		//Disable interrupt

	EPwm1Regs.ETPS.all = 0x0101;
	/*
	bit 9-8   01		SOCAPRD		generate the EPWMxSOCA pulse on the first event ETPS.SOCACNT=01
	bit	1-0	  01:		INTPRD		generate an interrupt on the first event
	*/
	//EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;			//generate an interrupt on the first event
	//EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST;
     
   
}


void InitEPwm2Example()
{

  
		EPwm2Regs.TBCTL.all = 0x2006;
  	/*
	bit	15-14	00:		FREE,SOFT
	bit	13		1:  	PHSDIR
	bit	12-10	000:	CLKDIV
	bit	9-7		000:	HSPCLKDIV
	bit	6		0:		SWFSYNC
	bit 5-4		00:		SYNCOSEL	tb_ctr_zero
	bit 3		0:		PRDLD		loaded from shadow register
	bit 2		1:		PHSEN		enable
	bit 1-0		10:		CTRMODE		up and down
	*/
 	//EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
	//EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;
 	//EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
	//EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
	//EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	//EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
	//EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

	EPwm2Regs.TBPHS.half.TBPHS = 2;

	EPwm2Regs.AQCSFRC.all = 0x5;	// Force a continuous low on output EPWM2A and EPWM2B

	EPwm2Regs.AQCTLA.all = 0x0090;
	// bit 7-6		01:		CAD		force EPWMxA output low when counter decrements to CMPA
	// bit 5-4		10:		CAU		force EPWMxA output high when counter increments to CMPA

	EPwm2Regs.AQCTLB.all = 0x0060;
	// bit 7-6		10:		CAD		force EPWMxA output high when counter decrements to CMPA
	// bit 5-4		01:		CAU		force EPWMxA output low when counter increments to CMPA

	EPwm2Regs.CMPA.half.CMPA = 0;
	EPwm2Regs.TBCTR = 0;

//	EPwm2Regs.DBCTL.all = 0x000B;
	// bit 5-4: IN_MODE    00   EPWMxA is the source for the both rising-edge delay and falling-edge delay signal
	// bit 3-2: POLSEL	   10   Active low complementary mode
	// bit 1-0: OUT_MODE   11  Dead band is fully enabled for both rising-edge and falling-edge

//	EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
//	EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
//	EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
	EPwm2Regs.DBFED = 200;			// 200 * 16.67ns = 3.3us
	EPwm2Regs.DBRED = 200;			// 200 * 16.67ns = 3.3us
}

void InitEPwm3Example(void)
{

   EPwm3Regs.TBCTL.all = 0x2006;
  	/*
	bit	15-14	00:		FREE,SOFT
	bit	13		1:  	PHSDIR
	bit	12-10	000:	CLKDIV
	bit	9-7		000:	HSPCLKDIV
	bit	6		0:		SWFSYNC
	bit 5-4		00:		SYNCOSEL	tb_ctr_zero
	bit 3		0:		PRDLD		loaded from shadow register
	bit 2		1:		PHSEN		enable
	bit 1-0		10:		CTRMODE		up and down
	*/
 	//EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;
	//EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP;
 	//EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
	//EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
	//EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	//EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
	//EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;

	EPwm3Regs.TBPHS.half.TBPHS = 2;

	EPwm3Regs.AQCSFRC.all = 0x5;	// Force a continuous low on output EPWM3A and EPWM3B

	EPwm3Regs.AQCTLA.all = 0x0090;
	// bit 7-6		01:		CAD		force EPWMxA output low when counter decrements to CMPA
	// bit 5-4		10:		CAU		force EPWMxA output high when counter increments to CMPA

	EPwm3Regs.AQCTLB.all = 0x0060;
	// bit 7-6		10:		CAD		force EPWMxB output high when counter decrements to CMPA
	// bit 5-4		01:		CAU		force EPWMxB output low when counter increments to CMPA

	EPwm3Regs.CMPA.half.CMPA = 0;
	EPwm3Regs.TBCTR = 0;

//	EPwm3Regs.DBCTL.all = 0x000B;
	// bit 5-4: IN_MODE    00   EPWMxA is the source for the both rising-edge delay and falling-edge delay signal
	// bit 3-2: POLSEL	   10   Active low complementary mode
	// bit 1-0: OUT_MODE   11  Dead band is fully enabled for both rising-edge and falling-edge

//	EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
//	EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
//	EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
	EPwm3Regs.DBFED = 200;			// 200 * 16.67ns = 3.3us
	EPwm3Regs.DBRED = 200;			// 200 * 16.67ns = 3.3us    
   
}




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// End of file.
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