📄 blink.lst
字号:
008F +1 212 TF1 BIT 08FH ; TIMER 1 OVERFLOW FLAG
008E +1 213 TR1 BIT 08EH ; TIMER 1 ON/OFF CONTROL
008D +1 214 TF0 BIT 08DH ; TIMER 0 OVERFLOW FLAG
008C +1 215 TR0 BIT 08CH ; TIMER 0 ON/OFF CONTROL
008B +1 216 IE1 BIT 08BH ; EXT. INTERRUPT 1 EDGE FLAG
008A +1 217 IT1 BIT 08AH ; EXT. INTERRUPT 1 TYPE
0089 +1 218 IE0 BIT 089H ; EXT. INTERRUPT 0 EDGE FLAG
0088 +1 219 IT0 BIT 088H ; EXT. INTERRUPT 0 TYPE
+1 220
+1 221 ; CPT0CN 088H
008F +1 222 CP0EN BIT 08FH ; COMPARATOR 0 ENABLE
008E +1 223 CP0OUT BIT 08EH ; COMPARATOR 0 OUTPUT
008D +1 224 CP0RIF BIT 08DH ; COMPARATOR 0 RISING EDGE INTERRUPT
008C +1 225 CP0FIF BIT 08CH ; COMPARATOR 0 FALLING EDGE INTERRUPT
008B +1 226 CP0HYP1 BIT 08BH ; COMPARATOR 0 POSITIVE HYSTERISIS 1
008A +1 227 CP0HYP0 BIT 08AH ; COMPARATOR 0 POSITIVE HYSTERISIS 0
0089 +1 228 CP0HYN1 BIT 089H ; COMPARATOR 0 NEGATIVE HYSTERISIS 1
0088 +1 229 CP0HYN0 BIT 088H ; COMPARATOR 0 NEGATIVE HYSTERISIS 0
+1 230
+1 231 ; CPT1CN 088H
008F +1 232 CP1EN BIT 08FH ; COMPARATOR 1 ENABLE
008E +1 233 CP1OUT BIT 08EH ; COMPARATOR 1 OUTPUT
008D +1 234 CP1RIF BIT 08DH ; COMPARATOR 1 RISING EDGE INTERRUPT
008C +1 235 CP1FIF BIT 08CH ; COMPARATOR 1 FALLING EDGE INTERRUPT
008B +1 236 CP1HYP1 BIT 08BH ; COMPARATOR 1 POSITIVE HYSTERISIS 1
008A +1 237 CP1HYP0 BIT 08AH ; COMPARATOR 1 POSITIVE HYSTERISIS 0
0089 +1 238 CP1HYN1 BIT 089H ; COMPARATOR 1 NEGATIVE HYSTERISIS 1
0088 +1 239 CP1HYN0 BIT 088H ; COMPARATOR 1 NEGATIVE HYSTERISIS 0
+1 240
+1 241 ; CPT2CN 088H
008F +1 242 CP2EN BIT 08FH ; COMPARATOR 2 ENABLE
008E +1 243 CP2OUT BIT 08EH ; COMPARATOR 2 OUTPUT
008D +1 244 CP2RIF BIT 08DH ; COMPARATOR 2 RISING EDGE INTERRUPT
008C +1 245 CP2FIF BIT 08CH ; COMPARATOR 2 FALLING EDGE INTERRUPT
008B +1 246 CP2HYP1 BIT 08BH ; COMPARATOR 2 POSITIVE HYSTERISIS 1
008A +1 247 CP2HYP0 BIT 08AH ; COMPARATOR 2 POSITIVE HYSTERISIS 0
0089 +1 248 CP2HYN1 BIT 089H ; COMPARATOR 2 NEGATIVE HYSTERISIS 1
0088 +1 249 CP2HYN0 BIT 088H ; COMPARATOR 2 NEGATIVE HYSTERISIS 0
+1 250
+1 251 ; SCON0 098H
009F +1 252 SM00 BIT 09FH ; UART 0 MODE 0
009E +1 253 SM10 BIT 09EH ; UART 0 MODE 1
009D +1 254 SM20 BIT 09DH ; UART 0 MULTIPROCESSOR EN
009C +1 255 REN0 BIT 09CH ; UART 0 RX ENABLE
009B +1 256 TB80 BIT 09BH ; UART 0 TX BIT 8
A51 MACRO ASSEMBLER BLINK 06/14/2005 10:06:17 PAGE 5
009A +1 257 RB80 BIT 09AH ; UART 0 RX BIT 8
0099 +1 258 TI0 BIT 099H ; UART 0 TX INTERRUPT FLAG
0098 +1 259 RI0 BIT 098H ; UART 0 RX INTERRUPT FLAG
+1 260
+1 261 ; SCON1 098H
009F +1 262 S1MODE BIT 09FH ; UART 1 MODE
009D +1 263 MCE1 BIT 09DH ; UART 1 MCE
009C +1 264 REN1 BIT 09CH ; UART 1 RX ENABLE
009B +1 265 TB81 BIT 09BH ; UART 1 TX BIT 8
009A +1 266 RB81 BIT 09AH ; UART 1 RX BIT 8
0099 +1 267 TI1 BIT 099H ; UART 1 TX INTERRUPT FLAG
0098 +1 268 RI1 BIT 098H ; UART 1 RX INTERRUPT FLAG
+1 269
+1 270 ; IE 0A8H
00AF +1 271 EA BIT 0AFH ; GLOBAL INTERRUPT ENABLE
00AD +1 272 ET2 BIT 0ADH ; TIMER 2 INTERRUPT ENABLE
00AC +1 273 ES0 BIT 0ACH ; UART0 INTERRUPT ENABLE
00AB +1 274 ET1 BIT 0ABH ; TIMER 1 INTERRUPT ENABLE
00AA +1 275 EX1 BIT 0AAH ; EXTERNAL INTERRUPT 1 ENABLE
00A9 +1 276 ET0 BIT 0A9H ; TIMER 0 INTERRUPT ENABLE
00A8 +1 277 EX0 BIT 0A8H ; EXTERNAL INTERRUPT 0 ENABLE
+1 278
+1 279 ; IP 0B8H
00BD +1 280 PT2 BIT 0BDH ; TIMER 2 PRIORITY
00BC +1 281 PS BIT 0BCH ; SERIAL PORT PRIORITY
00BB +1 282 PT1 BIT 0BBH ; TIMER 1 PRIORITY
00BA +1 283 PX1 BIT 0BAH ; EXTERNAL INTERRUPT 1 PRIORITY
00B9 +1 284 PT0 BIT 0B9H ; TIMER 0 PRIORITY
00B8 +1 285 PX0 BIT 0B8H ; EXTERNAL INTERRUPT 0 PRIORITY
+1 286
+1 287 ; CAN0STA 0C0H
00C7 +1 288 BOFF BIT 0C7H ; BUS OFF STATUS
00C6 +1 289 EWARN BIT 0C6H ; WARNING STATUS
00C5 +1 290 EPASS BIT 0C5H ; ERROR PASSIVE
00C4 +1 291 RXOK BIT 0C4H ; RECEIVED MESSAGE SUCCESSFULLY
00C3 +1 292 TXOK BIT 0C3H ; TRANSMIT A MESSAGE SUCCESSFULLY
00C2 +1 293 LEC2 BIT 0C2H ; LAST ERROR CODE BIT 2
00C1 +1 294 LEC1 BIT 0C1H ; LAST ERROR CODE BIT 1
00C0 +1 295 LEC0 BIT 0C0H ; LAST ERROR CODE BIT 0
+1 296
+1 297 ; SMB0CN 0C0H
00C7 +1 298 BUSY BIT 0C7H ; SMBUS 0 BUSY
00C6 +1 299 ENSMB BIT 0C6H ; SMBUS 0 ENABLE
00C5 +1 300 STA BIT 0C5H ; SMBUS 0 START FLAG
00C4 +1 301 STO BIT 0C4H ; SMBUS 0 STOP FLAG
00C3 +1 302 SI BIT 0C3H ; SMBUS 0 INTERRUPT PENDING FLAG
00C2 +1 303 AA BIT 0C2H ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG
00C1 +1 304 SMBFTE BIT 0C1H ; SMBUS 0 FREE TIMER ENABLE
00C0 +1 305 SMBTOE BIT 0C0H ; SMBUS 0 TIMEOUT ENABLE
+1 306
+1 307 ; TMR2CN 0C8H
00CF +1 308 TF2 BIT 0CFH ; TIMER 2 OVERFLOW FLAG
00CE +1 309 EXF2 BIT 0CEH ; TIMER 2 EXTERNAL FLAG
00CB +1 310 EXEN2 BIT 0CBH ; TIMER 2 EXTERNAL ENABLE FLAG
00CA +1 311 TR2 BIT 0CAH ; TIMER 2 ON/OFF CONTROL
00C9 +1 312 CT2 BIT 0C9H ; TIMER 2 COUNTER SELECT
00C8 +1 313 CPRL2 BIT 0C8H ; TIMER 2 CAPTURE SELECT
+1 314
+1 315 ; TMR3CN 0C8H
00CF +1 316 TF3 BIT 0CFH ; TIMER 3 OVERFLOW FLAG
00CE +1 317 EXF3 BIT 0CEH ; TIMER 3 EXTERNAL FLAG
00CB +1 318 EXEN3 BIT 0CBH ; TIMER 3 EXTERNAL ENABLE FLAG
00CA +1 319 TR3 BIT 0CAH ; TIMER 3 ON/OFF CONTROL
00C9 +1 320 CT3 BIT 0C9H ; TIMER 3 COUNTER SELECT
00C8 +1 321 CPRL3 BIT 0C8H ; TIMER 3 CAPTURE SELECT
+1 322
A51 MACRO ASSEMBLER BLINK 06/14/2005 10:06:17 PAGE 6
+1 323 ; TMR4CN 0C8H
00CF +1 324 TF4 BIT 0CFH ; TIMER 4 OVERFLOW FLAG
00CE +1 325 EXF4 BIT 0CEH ; TIMER 4 EXTERNAL FLAG
00CB +1 326 EXEN4 BIT 0CBH ; TIMER 4 EXTERNAL ENABLE FLAG
00CA +1 327 TR4 BIT 0CAH ; TIMER 4 ON/OFF CONTROL
00C9 +1 328 CT4 BIT 0C9H ; TIMER 4 COUNTER SELECT
00C8 +1 329 CPRL4 BIT 0C8H ; TIMER 4 CAPTURE SELECT
+1 330
+1 331 ; PSW 0D0H
00D7 +1 332 CY BIT 0D7H ; CARRY FLAG
00D6 +1 333 AC BIT 0D6H ; AUXILIARY CARRY FLAG
00D5 +1 334 F0 BIT 0D5H ; USER FLAG 0
00D4 +1 335 RS1 BIT 0D4H ; REGISTER BANK SELECT 1
00D3 +1 336 RS0 BIT 0D3H ; REGISTER BANK SELECT 0
00D2 +1 337 OV BIT 0D2H ; OVERFLOW FLAG
00D1 +1 338 F1 BIT 0D1H ; USER FLAG 1
00D0 +1 339 P BIT 0D0H ; ACCUMULATOR PARITY FLAG
+1 340
+1 341 ; DMA0CN 0D8H
00DF +1 342 DMA0EN BIT 0DFH ; DMA 0 ENABLE
00DE +1 343 DMA0INT BIT 0DEH ; DMA 0 OPERATIONS COMPLETE
00DD +1 344 DMA0MD BIT 0DDH ; DMA 0 MODE SELECT
00DC +1 345 DMA0DE1 BIT 0DCH ; ADC 0 DATA OVERFLOW ERROR
00DB +1 346 DMA0DE0 BIT 0DBH ; ADC 1 DATA OVERFLOW ERROR
00DA +1 347 DMA0DOE BIT 0DAH ; DMA 0 DATA OVERFLOW WARNINGENABLE
00D9 +1 348 DMA0DO1 BIT 0D9H ; ADC 0 DATA OVERFLOW WARNING
00D8 +1 349 DMA0DO0 BIT 0D8H ; ADC 1 DATA OVERFLOW WARNING
+1 350
+1 351 ; PCA0CN 0D8H
00DF +1 352 CF BIT 0DFH ; PCA 0 COUNTER OVERFLOW FLAG
00DE +1 353 CR BIT 0DEH ; PCA 0 COUNTER RUN CONTROL BIT
00DD +1 354 CCF5 BIT 0DDH ; PCA 0 MODULE 5 INTERRUPT FLAG
00DC +1 355 CCF4 BIT 0DCH ; PCA 0 MODULE 4 INTERRUPT FLAG
00DB +1 356 CCF3 BIT 0DBH ; PCA 0 MODULE 3 INTERRUPT FLAG
00DA +1 357 CCF2 BIT 0DAH ; PCA 0 MODULE 2 INTERRUPT FLAG
00D9 +1 358 CCF1 BIT 0D9H ; PCA 0 MODULE 1 INTERRUPT FLAG
00D8 +1 359 CCF0 BIT 0D8H ; PCA 0 MODULE 0 INTERRUPT FLAG
+1 360
+1 361 ; ADC0CN 0E8H
00EF +1 362 AD0EN BIT 0EFH ; ADC 0 ENABLE
00EE +1 363 AD0TM BIT 0EEH ; ADC 0 TRACK MODE
00ED +1 364 AD0INT BIT 0EDH ; ADC 0 EOC INTERRUPT FLAG
00EC +1 365 AD0BUSY BIT 0ECH ; ADC 0 BUSY FLAG
00EB +1 366 AD0CM1 BIT 0EBH ; ADC 0 CONVERT START MODE BIT 1
00EA +1 367 AD0CM0 BIT 0EAH ; ADC 0 CONVERT START MODE BIT 0
00E9 +1 368 AD0WINT BIT 0E9H ; ADC 0 WINDOW INTERRUPT FLAG
+1 369
+1 370 ; ADC1CN 0E8H
00EF +1 371 AD1EN BIT 0EFH ; ADC 1 ENABLE
00EE +1 372 AD1TM BIT 0EEH ; ADC 1 TRACK MODE
00ED +1 373 AD1INT BIT 0EDH ; ADC 1 EOC INTERRUPT FLAG
00EC +1 374 AD1BUSY BIT 0ECH ; ADC 1 BUSY FLAG
00EB +1 375 AD1CM2 BIT 0EBH ; ADC 1 CONVERT START MODE BIT 2
00EA +1 376 AD1CM1 BIT 0EAH ; ADC 1 CONVERT START MODE BIT 1
00E9 +1 377 AD1CM0 BIT 0E9H ; ADC 1 CONVERT START MODE BIT 0
+1 378
+1 379 ; ADC2CN 0E8H
00EF +1 380 AD2EN BIT 0EFH ; ADC 2 ENABLE
00EE +1 381 AD2TM BIT 0EEH ; ADC 2 TRACK MODE
00ED +1 382 AD2INT BIT 0EDH ; ADC 2 EOC INTERRUPT FLAG
00EC +1 383 AD2BUSY BIT 0ECH ; ADC 2 BUSY FLAG
00EB +1 384 AD2CM1 BIT 0EBH ; ADC 2 CONVERT START MODE BIT 1
00EA +1 385 AD2CM0 BIT 0EAH ; ADC 2 CONVERT START MODE BIT 0
00E9 +1 386 AD2WINT BIT 0E9H ; ADC 2 WINDOW INTERRUPT FLAG
00E8 +1 387 AD2LJST BIT 0E8H ; ADC 2 LEFT JUSTIFY DATA BIT
+1 388
A51 MACRO ASSEMBLER BLINK 06/14/2005 10:06:17 PAGE 7
+1 389 ; DMA0CF 0F8H
00FF +1 390 DMA0HLT BIT 0FFH ; DMA 0 HALT OFF-CHIP XRAM ENABLE
00FE +1 391 DMA0XBY BIT 0FEH ; DMA 0 XRAM BUSY
00FB +1 392 DMA0CIE BIT 0FBH ; DMA 0 COUNTER OVERFLOW ENABLE
00FA +1 393 DMA0CI BIT 0FAH ; DMA 0 COUNTER OVERFLOW
00F9 +1 394 DMA0EOE BIT 0F9H ; DMA 0 END OF OPERATION ENABLE
00F8 +1 395 DMA0EO BIT 0F8H ; DMA 0 END OF OPERATION
+1 396
+1 397 ; SPI0CN 0F8H
00FF +1 398 SPIF BIT 0FFH ; SPI 0 INTERRUPT FLAG
00FE +1 399 WCOL BIT 0FEH ; SPI 0 WRITE COLLISION FLAG
00FD +1 400 MODF BIT 0FDH ; SPI 0 MODE FAULT FLAG
00FC +1 401 RXOVRN BIT 0FCH ; SPI 0 RX OVERRUN FLAG
00FB +1 402 NSSMD1 BIT 0FBH ; SPI 0 SLAVE SELECT MODE 1
00FA +1 403 NSSMD0 BIT 0FAH ; SPI 0 SLAVE SELECT MODE 0
00F9 +1 404 TXBMT BIT 0F9H ; SPI 0 TX BUFFER EMPTY FLAG
00F8 +1 405 SPIEN BIT 0F8H ; SPI 0 SPI ENABLE
+1 406
+1 407 ;
+1 408 ;------------------------------------------------------------------------------
+1 409 ; SFR PAGE DEFINITIONS
+1 410 ;
000F +1 411 CONFIG_PAGE EQU 0FH ; SYSTEM AND PORT CONFIGURATION PAGE
0000 +1 412 LEGACY_PAGE EQU 00H ; LEGACY SFR PAGE
0000 +1 413 TIMER01_PAGE EQU 00H ; TIMER 0 AND TIMER 1
0001 +1 414 CPT0_PAGE EQU 01H ; COMPARATOR 0
0002 +1 415 CPT1_PAGE EQU 02H ; COMPARATOR 1
0003 +1 416 CPT2_PAGE EQU 03H ; COMPARATOR 2
0000 +1 417 UART0_PAGE EQU 00H ; UART 0
0001 +1 418 UART1_PAGE EQU 01H ; UART 1
0000 +1 419 SPI0_PAGE EQU 00H ; SPI 0
0000 +1 420 EMI0_PAGE EQU 00H ; EXTERNAL MEMORY INTERFACE
0000 +1 421 ADC0_PAGE EQU 00H ; ADC 0
0001 +1 422 ADC1_PAGE EQU 01H ; ADC 1
0002 +1 423 ADC2_PAGE EQU 02H ; ADC 2
0000 +1 424 SMB0_PAGE EQU 00H ; SMBUS 0
0000 +1 425 TMR2_PAGE EQU 00H ; TIMER 2
0001 +1 426 TMR3_PAGE EQU 01H ; TIMER 3
0002 +1 427 TMR4_PAGE EQU 02H ; TIMER 4
0000 +1 428 DAC0_PAGE EQU 00H ; DAC 0
0001 +1 429 DAC1_PAGE EQU 01H ; DAC 1
0000 +1 430 PCA0_PAGE EQU 00H ; PCA 0
0003 +1 431 DMA0_PAGE EQU 03H ; DMA 0
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