📄 blink.lst
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A51 MACRO ASSEMBLER BLINK 06/14/2005 10:06:17 PAGE 1
MACRO ASSEMBLER A51 V7.04a
OBJECT MODULE PLACED IN blink.OBJ
ASSEMBLER INVOKED BY: C:\SiLabs\MCU\IDEfiles\C51\BIN\a51.exe blink.asm XR GEN DB EP NOMOD51
LOC OBJ LINE SOURCE
1 ;-----------------------------------------------------------------------------
2 ; Copyright (C) 2004 Silicon Laboratories, Inc.
3 ; All rights reserved.
4 ;
5 ;
6 ;
7 ; FILE NAME : BLINK.ASM
8 ; TARGET MCU : C8051F060/1/2/3
9 ; DESCRIPTION : This program illustrates how to disable the watchdog timer,
10 ; configure a port and write to a port I/O pin.
11 ;
12 ; NOTES:
13 ;
14 ;-----------------------------------------------------------------------------
15
16 ;$include (c8051f060.inc) ; Include register definition file.
+1 17 ;---------------------------------------------------------------------------
+1 18 ;
+1 19 ;
+1 20 ;
+1 21 ;
+1 22 ; FILE NAME: C8051F060.INC
+1 23 ; TARGET MCUs: C8051F060, F061, F062, F063
+1 24 ; DESCRIPTION: Register/bit definitions for the C8051F060 product family.
+1 25 ;
+1 26 ; REVISION 1.2
+1 27 ;
+1 28 ;---------------------------------------------------------------------------
+1 29
+1 30 ;REGISTER DEFINITIONS
+1 31 ;
0080 +1 32 P0 DATA 080H ; PORT 0 LATCH
0081 +1 33 SP DATA 081H ; STACK POINTER
0082 +1 34 DPL DATA 082H ; DATA POINTER LOW
0083 +1 35 DPH DATA 083H ; DATA POINTER HIGH
0084 +1 36 SFRPAGE DATA 084H ; SFR PAGE REGISTER
0085 +1 37 SFRNEXT DATA 085H ; SFR PAGE REGISTER
0086 +1 38 SFRLAST DATA 086H ; SFR PAGE STACK ACCESS REGISTER
0087 +1 39 PCON DATA 087H ; POWER CONTROL
0088 +1 40 CPT0CN DATA 088H ; COMPARATOR 0 CONTROL
0088 +1 41 CPT1CN DATA 088H ; COMPARATOR 1 CONTROL
0088 +1 42 CPT2CN DATA 088H ; COMPARATOR 2 CONTROL
0088 +1 43 TCON DATA 088H ; TIMER/COUNTER CONTROL
0089 +1 44 CPT0MD DATA 089H ; COMPARATOR 0 CONFIGURATION
0089 +1 45 CPT1MD DATA 089H ; COMPARATOR 1 CONFIGURATION
0089 +1 46 CPT2MD DATA 089H ; COMPARATOR 2 CONFIGURATION
0089 +1 47 TMOD DATA 089H ; TIMER/COUNTER MODE
008A +1 48 OSCICN DATA 08AH ; INTERNAL OSCILLATOR CONTROL
008A +1 49 TL0 DATA 08AH ; TIMER/COUNTER 0 LOW
008B +1 50 OSCICL DATA 08BH ; INTERNAL OSCILLATOR CALIBRATION
008B +1 51 TL1 DATA 08BH ; TIMER/COUNTER 1 LOW
008C +1 52 OSCXCN DATA 08CH ; EXTERNAL OSCILLATOR CONTROL
008C +1 53 TH0 DATA 08CH ; TIMER/COUNTER 0 HIGH
008D +1 54 TH1 DATA 08DH ; TIMER/COUNTER 1 HIGH
008E +1 55 CKCON DATA 08EH ; CLOCK CONTROL
008F +1 56 PSCTL DATA 08FH ; PROGRAM STORE R/W CONTROL
0090 +1 57 P1 DATA 090H ; PORT 1 LATCH
0091 +1 58 SSTA0 DATA 091H ; UART 0 STATUS
A51 MACRO ASSEMBLER BLINK 06/14/2005 10:06:17 PAGE 2
0096 +1 59 SFRPGCN DATA 096H ; SFR PAGE CONTROL REGISTER
0097 +1 60 CLKSEL DATA 097H ; OSCILLATOR CLOCK SELECTION REGISTER
0098 +1 61 SCON0 DATA 098H ; UART 0 CONTROL
0098 +1 62 SCON1 DATA 098H ; UART 1 CONTROL
0099 +1 63 SBUF0 DATA 099H ; UART 0 DATA BUFFER
0099 +1 64 SBUF1 DATA 099H ; UART 1 DATA BUFFER
009A +1 65 SPI0CFG DATA 09AH ; SPI CONFIGURATION
009B +1 66 SPI0DAT DATA 09BH ; SPI DATA
009C +1 67 P4MDOUT DATA 09CH ; PORT 4 OUTPUT MODE CONFIGURATION
009D +1 68 P5MDOUT DATA 09DH ; PORT 5 OUTPUT MODE CONFIGURATION
009D +1 69 SPI0CKR DATA 09DH ; SPI CLOCK RATE CONTROL
009E +1 70 P6MDOUT DATA 09EH ; PORT 6 OUTPUT MODE CONFIGURATION
009F +1 71 P7MDOUT DATA 09FH ; PORT 7 OUTPUT MODE CONFIGURATION
00A0 +1 72 P2 DATA 0A0H ; PORT 2 LATCH
00A1 +1 73 EMI0TC DATA 0A1H ; EMIF TIMING CONTROL
00A2 +1 74 EMI0CN DATA 0A2H ; EMIF CONTROL
00A3 +1 75 EMI0CF DATA 0A3H ; EMIF CONFIGURATION
00A4 +1 76 P0MDOUT DATA 0A4H ; PORT 0 OUTPUT MODE CONFIGURATION
00A5 +1 77 P1MDOUT DATA 0A5H ; PORT 1 OUTPUT MODE CONFIGURATION
00A6 +1 78 P2MDOUT DATA 0A6H ; PORT 2 OUTPUT MODE CONFIGURATION
00A7 +1 79 P3MDOUT DATA 0A7H ; PORT 3 OUTPUT MODE CONFIGURATION
00A8 +1 80 IE DATA 0A8H ; INTERRUPT ENABLE
00A9 +1 81 SADDR0 DATA 0A9H ; UART 0 SLAVE ADDRESS
00AD +1 82 P1MDIN DATA 0ADH ; PORT 1 INPUT MODE
00AE +1 83 P2MDIN DATA 0AEH ; PORT 2 INPUT MODE
00B0 +1 84 P3 DATA 0B0H ; PORT 3 LATCH
00B7 +1 85 FLACL DATA 0B7H ; FLASH ACCESS LIMIT
00B7 +1 86 FLSCL DATA 0B7H ; FLASH SCALE
00B8 +1 87 IP DATA 0B8H ; INTERRUPT PRIORITY
00B9 +1 88 SADEN0 DATA 0B9H ; UART 0 SLAVE ADDRESS ENABLE
00BA +1 89 ADC0CPT DATA 0BAH ; ADC0 CALIBRATION POINTER
00BA +1 90 AMX2CF DATA 0BAH ; ADC2 ANALOG MULTIPLEXER CONFIGURATION
00BB +1 91 ADC0CCF DATA 0BBH ; ADC0 CALIBRATION COEFFICIENT
00BB +1 92 AMX0SL DATA 0BBH ; ADC0 MULTIPLEXER CHANNEL SELECT
00BB +1 93 AMX2SL DATA 0BBH ; ADC2 ANALOG MULTIPLEXER CHANNEL SELECT
00BC +1 94 ADC0CF DATA 0BCH ; ADC0 CONFIGURATION
00BC +1 95 ADC1CF DATA 0BCH ; ADC1 CONFIGURATION
00BC +1 96 ADC2CF DATA 0BCH ; ADC2 CONFIGURATION
00BE +1 97 ADC0L DATA 0BEH ; ADC0 DATA WORD LOW
00BE +1 98 ADC1L DATA 0BEH ; ADC1 DATA WORD LOW
00BE +1 99 ADC2L DATA 0BEH ; ADC2 DATA WORD LOW
00BF +1 100 ADC0H DATA 0BFH ; ADC0 DATA WORD HIGH
00BF +1 101 ADC1H DATA 0BFH ; ADC1 DATA WORD HIGH
00BF +1 102 ADC2H DATA 0BFH ; ADC2 DATA WORD HIGH
00C0 +1 103 CAN0STA DATA 0C0H ; CAN0 STATUS
00C0 +1 104 SMB0CN DATA 0C0H ; SMBUS CONTROL
00C1 +1 105 SMB0STA DATA 0C1H ; SMBUS STATUS
00C2 +1 106 SMB0DAT DATA 0C2H ; SMBUS DATA
00C3 +1 107 SMB0ADR DATA 0C3H ; SMBUS SLAVE ADDRESS
00C4 +1 108 ADC0GTL DATA 0C4H ; ADC0 GREATER-THAN LOW
00C4 +1 109 ADC2GTL DATA 0C4H ; ADC2 GREATER-THAN LOW
00C5 +1 110 ADC0GTH DATA 0C5H ; ADC0 GREATER-THAN HIGH
00C5 +1 111 ADC2GTH DATA 0C5H ; ADC2 GREATER-THAN HIGH
00C6 +1 112 ADC0LTL DATA 0C6H ; ADC0 LESS-THAN LOW
00C6 +1 113 ADC2LTL DATA 0C6H ; ADC2 LESS-THAN LOW
00C7 +1 114 ADC0LTH DATA 0C7H ; ADC0 LESS-THAN HIGH
00C7 +1 115 ADC2LTH DATA 0C7H ; ADC2 LESS-THAN HIGH
00C8 +1 116 P4 DATA 0C8H ; PORT 4 LATCH
00C8 +1 117 TMR2CN DATA 0C8H ; TIMER/COUNTER 2 CONTROL
00C8 +1 118 TMR3CN DATA 0C8H ; TIMER/COUNTER 3 CONTROL
00C8 +1 119 TMR4CN DATA 0C8H ; TIMER/COUNTER 4 CONTROL
00C9 +1 120 TMR2CF DATA 0C9H ; TIMER/COUNTER 2 CONFIGURATION
00C9 +1 121 TMR3CF DATA 0C9H ; TIMER/COUNTER 3 CONFIGURATION
00C9 +1 122 TMR4CF DATA 0C9H ; TIMER/COUNTER 4 CONFIGURATION
00CA +1 123 RCAP2L DATA 0CAH ; TIMER/COUNTER 2 CAPTURE/RELOAD LOW
00CA +1 124 RCAP3L DATA 0CAH ; TIMER/COUNTER 3 CAPTURE/RELOAD LOW
A51 MACRO ASSEMBLER BLINK 06/14/2005 10:06:17 PAGE 3
00CA +1 125 RCAP4L DATA 0CAH ; TIMER/COUNTER 4 CAPTURE/RELOAD LOW
00CB +1 126 RCAP2H DATA 0CBH ; TIMER/COUNTER 2 CAPTURE/RELOAD HIGH
00CB +1 127 RCAP3H DATA 0CBH ; TIMER/COUNTER 3 CAPTURE/RELOAD HIGH
00CB +1 128 RCAP4H DATA 0CBH ; TIMER/COUNTER 4 CAPTURE/RELOAD HIGH
00CC +1 129 TMR2L DATA 0CCH ; TIMER/COUNTER 2 LOW
00CC +1 130 TMR3L DATA 0CCH ; TIMER/COUNTER 3 LOW
00CC +1 131 TMR4L DATA 0CCH ; TIMER/COUNTER 4 LOW
00CD +1 132 TMR2H DATA 0CDH ; TIMER/COUNTER 2 HIGH
00CD +1 133 TMR3H DATA 0CDH ; TIMER/COUNTER 3 HIGH
00CD +1 134 TMR4H DATA 0CDH ; TIMER/COUNTER 4 HIGH
00CF +1 135 SMB0CR DATA 0CFH ; SMBUS CLOCK RATE
00D0 +1 136 PSW DATA 0D0H ; PROGRAM STATUS WORD
00D1 +1 137 REF0CN DATA 0D1H ; VOLTAGE REFERENCE CONTROL 0
00D1 +1 138 REF1CN DATA 0D1H ; VOLTAGE REFERENCE CONTROL 1
00D1 +1 139 REF2CN DATA 0D1H ; VOLTAGE REFERENCE CONTROL 2
00D2 +1 140 DAC0L DATA 0D2H ; DAC0 LOW
00D2 +1 141 DAC1L DATA 0D2H ; DAC1 LOW
00D3 +1 142 DAC0H DATA 0D3H ; DAC0 HIGH
00D3 +1 143 DAC1H DATA 0D3H ; DAC1 HIGH
00D4 +1 144 DAC0CN DATA 0D4H ; DAC0 CONTROL
00D4 +1 145 DAC1CN DATA 0D4H ; DAC1 CONTROL
00D8 +1 146 CAN0DATL DATA 0D8H ; CAN0 DATA LOW
00D8 +1 147 DMA0CN DATA 0D8H ; DMA0 CONTROL
00D8 +1 148 P5 DATA 0D8H ; PORT 5 LATCH
00D8 +1 149 PCA0CN DATA 0D8H ; PCA CONTROL
00D9 +1 150 CAN0DATH DATA 0D9H ; CAN0 DATA HIGH
00D9 +1 151 DMA0DAL DATA 0D9H ; DMA0 DATA ADDRESS BEGINNING LOW BYTE
00D9 +1 152 PCA0MD DATA 0D9H ; PCA MODE
00DA +1 153 CAN0ADR DATA 0DAH ; CAN0 ADDRESS
00DA +1 154 DMA0DAH DATA 0DAH ; DMA0 DATA ADDRESS BEGINNING HIGH BYTE
00DA +1 155 PCA0CPM0 DATA 0DAH ; PCA MODULE 0 MODE REGISTER
00DB +1 156 CAN0TST DATA 0DBH ; CAN0 TEST
00DB +1 157 DMA0DSL DATA 0DBH ; DMA0 DATA ADDRESS POINTER LOW BYTE
00DB +1 158 PCA0CPM1 DATA 0DBH ; PCA MODULE 1 MODE REGISTER
00DC +1 159 DMA0DSH DATA 0DCH ; DMA0 DATA ADDRESS POINTER HIGH BYTE
00DC +1 160 PCA0CPM2 DATA 0DCH ; PCA MODULE 2 MODE REGISTER
00DD +1 161 DMA0IPT DATA 0DDH ; DMA0 INSTRUCTION WRITE ADDRESS
00DD +1 162 PCA0CPM3 DATA 0DDH ; PCA MODULE 3 MODE REGISTER
00DE +1 163 DMA0IDT DATA 0DEH ; DMA0 INSTRUCTION WRITE DATA
00DE +1 164 PCA0CPM4 DATA 0DEH ; PCA MODULE 4 MODE REGISTER
00DF +1 165 PCA0CPM5 DATA 0DFH ; PCA MODULE 5 MODE REGISTER
00E0 +1 166 ACC DATA 0E0H ; ACCUMULATOR
00E1 +1 167 PCA0CPL5 DATA 0E1H ; PCA CAPTURE 5 LOW
00E1 +1 168 XBR0 DATA 0E1H ; PORT I/O CROSSBAR CONTROL 0
00E2 +1 169 PCA0CPH5 DATA 0E2H ; PCA CAPTURE 5 HIGH
00E2 +1 170 XBR1 DATA 0E2H ; PORT I/O CROSSBAR CONTROL 1
00E3 +1 171 XBR2 DATA 0E3H ; PORT I/O CROSSBAR CONTROL 2
00E4 +1 172 XBR3 DATA 0E4H ; PORT I/O CROSSBAR CONTROL 3
00E6 +1 173 EIE1 DATA 0E6H ; EXTENDED INTERRUPT ENABLE 1
00E7 +1 174 EIE2 DATA 0E7H ; EXTENDED INTERRUPT ENABLE 2
00E8 +1 175 ADC0CN DATA 0E8H ; ADC0 CONTROL
00E8 +1 176 ADC1CN DATA 0E8H ; ADC1 CONTROL
00E8 +1 177 ADC2CN DATA 0E8H ; ADC2 CONTROL
00E8 +1 178 P6 DATA 0E8H ; PORT 6 LATCH
00E9 +1 179 PCA0CPL2 DATA 0E9H ; PCA CAPTURE 2 LOW
00EA +1 180 PCA0CPH2 DATA 0EAH ; PCA CAPTURE 2 HIGH
00EB +1 181 PCA0CPL3 DATA 0EBH ; PCA CAPTURE 3 LOW
00EC +1 182 PCA0CPH3 DATA 0ECH ; PCA CAPTURE 3 HIGH
00ED +1 183 PCA0CPL4 DATA 0EDH ; PCA CAPTURE 4 LOW
00EE +1 184 PCA0CPH4 DATA 0EEH ; PCA CAPTURE 4 HIGH
00EF +1 185 RSTSRC DATA 0EFH ; RESET SOURCE
00F0 +1 186 B DATA 0F0H ; B REGISTER
00F6 +1 187 EIP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY 1
00F7 +1 188 EIP2 DATA 0F7H ; EXTERNAL INTERRUPT PRIORITY 2
00F8 +1 189 CAN0CN DATA 0F8H ; CAN0 CONTROL
00F8 +1 190 DMA0CF DATA 0F8H ; DMA0 CONFIGURATION
A51 MACRO ASSEMBLER BLINK 06/14/2005 10:06:17 PAGE 4
00F8 +1 191 P7 DATA 0F8H ; PORT 7 LATCH
00F8 +1 192 SPI0CN DATA 0F8H ; SPI CONTROL
00F9 +1 193 DMA0CTL DATA 0F9H ; DMA0 REPEAT COUNTER LIMIT LOW BYTE
00F9 +1 194 PCA0L DATA 0F9H ; PCA COUNTER LOW
00FA +1 195 DMA0CTH DATA 0FAH ; DMA0 REPEAT COUNTER LIMIT HIGH BYTE
00FA +1 196 PCA0H DATA 0FAH ; PCA COUNTER HIGH
00FB +1 197 DMA0CSL DATA 0FBH ; DMA0 REPEAT COUNTER STATUS LOW BYTE
00FB +1 198 PCA0CPL0 DATA 0FBH ; PCA CAPTURE 0 LOW
00FC +1 199 DMA0CSH DATA 0FCH ; DMA0 REPEAT COUNTER STATUS HIGH BYTE
00FC +1 200 PCA0CPH0 DATA 0FCH ; PCA CAPTURE 0 HIGH
00FD +1 201 DMA0BND DATA 0FDH ; DMA0 INSTRUCTION BOUNDARY
00FD +1 202 PCA0CPL1 DATA 0FDH ; PCA CAPTURE 1 LOW
00FE +1 203 DMA0ISW DATA 0FEH ; DMA0 INSTRUCTION STATUS
00FE +1 204 PCA0CPH1 DATA 0FEH ; PCA CAPTURE 1 HIGH
00FF +1 205 WDTCN DATA 0FFH ; WATCHDOG TIMER CONTROL
+1 206
+1 207 ;
+1 208 ;------------------------------------------------------------------------------
+1 209 ;BIT DEFINITIONS
+1 210 ;
+1 211 ; TCON 088H
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