shub_mmr.h

鼎力推荐！本程序是基于嵌入式LUNUX系统开发的源程序代码

#define SH_RTC1_INT_CONFIG_AGT_SHFT              3
#define SH_RTC1_INT_CONFIG_AGT_MASK              0x0000000000000008

/*   SH_RTC1_INT_CONFIG_PID                                             */
/*   Description:  Processor ID, same setting as on targeted McKinley  */
#define SH_RTC1_INT_CONFIG_PID_SHFT              4
#define SH_RTC1_INT_CONFIG_PID_MASK              0x00000000000ffff0

/*   SH_RTC1_INT_CONFIG_BASE                                            */
/*   Description:  Optional interrupt vector area, 2MB aligned          */
#define SH_RTC1_INT_CONFIG_BASE_SHFT             21
#define SH_RTC1_INT_CONFIG_BASE_MASK             0x0003ffffffe00000

/*   SH_RTC1_INT_CONFIG_IDX                                             */
/*   Description:  Targeted McKinley interrupt vector                   */
#define SH_RTC1_INT_CONFIG_IDX_SHFT              52
#define SH_RTC1_INT_CONFIG_IDX_MASK              0x0ff0000000000000

/* ==================================================================== */
/*                    Register "SH_RTC1_INT_ENABLE"                     */
/*                SHub RTC 1 Interrupt Enable Registers                 */
/* ==================================================================== */

#define SH1_RTC1_INT_ENABLE                      0x0000000110001500
#define SH2_RTC1_INT_ENABLE                      0x0000000010001500
#define SH_RTC1_INT_ENABLE_MASK                  0x0000000000000001
#define SH_RTC1_INT_ENABLE_INIT                  0x0000000000000000

/*   SH_RTC1_INT_ENABLE_RTC1_ENABLE                                     */
/*   Description:  Enable RTC 1 Interrupt                               */
#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT      0
#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK      0x0000000000000001

/* ==================================================================== */
/*                    Register "SH_RTC2_INT_CONFIG"                     */
/*                SHub RTC 2 Interrupt Config Registers                 */
/* ==================================================================== */

#define SH1_RTC2_INT_CONFIG                      0x0000000110001580
#define SH2_RTC2_INT_CONFIG                      0x0000000010001580
#define SH_RTC2_INT_CONFIG_MASK                  0x0ff3ffffffefffff
#define SH_RTC2_INT_CONFIG_INIT                  0x0000000000000000

/*   SH_RTC2_INT_CONFIG_TYPE                                            */
/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
#define SH_RTC2_INT_CONFIG_TYPE_SHFT             0
#define SH_RTC2_INT_CONFIG_TYPE_MASK             0x0000000000000007

/*   SH_RTC2_INT_CONFIG_AGT                                             */
/*   Description:  Agent, must be 0 for SHub                            */
#define SH_RTC2_INT_CONFIG_AGT_SHFT              3
#define SH_RTC2_INT_CONFIG_AGT_MASK              0x0000000000000008

/*   SH_RTC2_INT_CONFIG_PID                                             */
/*   Description:  Processor ID, same setting as on targeted McKinley  */
#define SH_RTC2_INT_CONFIG_PID_SHFT              4
#define SH_RTC2_INT_CONFIG_PID_MASK              0x00000000000ffff0

/*   SH_RTC2_INT_CONFIG_BASE                                            */
/*   Description:  Optional interrupt vector area, 2MB aligned          */
#define SH_RTC2_INT_CONFIG_BASE_SHFT             21
#define SH_RTC2_INT_CONFIG_BASE_MASK             0x0003ffffffe00000

/*   SH_RTC2_INT_CONFIG_IDX                                             */
/*   Description:  Targeted McKinley interrupt vector                   */
#define SH_RTC2_INT_CONFIG_IDX_SHFT              52
#define SH_RTC2_INT_CONFIG_IDX_MASK              0x0ff0000000000000

/* ==================================================================== */
/*                    Register "SH_RTC2_INT_ENABLE"                     */
/*                SHub RTC 2 Interrupt Enable Registers                 */
/* ==================================================================== */

#define SH1_RTC2_INT_ENABLE                      0x0000000110001600
#define SH2_RTC2_INT_ENABLE                      0x0000000010001600
#define SH_RTC2_INT_ENABLE_MASK                  0x0000000000000001
#define SH_RTC2_INT_ENABLE_INIT                  0x0000000000000000

/*   SH_RTC2_INT_ENABLE_RTC2_ENABLE                                     */
/*   Description:  Enable RTC 2 Interrupt                               */
#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT      0
#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK      0x0000000000000001

/* ==================================================================== */
/*                    Register "SH_RTC3_INT_CONFIG"                     */
/*                SHub RTC 3 Interrupt Config Registers                 */
/* ==================================================================== */

#define SH1_RTC3_INT_CONFIG                      0x0000000110001680
#define SH2_RTC3_INT_CONFIG                      0x0000000010001680
#define SH_RTC3_INT_CONFIG_MASK                  0x0ff3ffffffefffff
#define SH_RTC3_INT_CONFIG_INIT                  0x0000000000000000

/*   SH_RTC3_INT_CONFIG_TYPE                                            */
/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
#define SH_RTC3_INT_CONFIG_TYPE_SHFT             0
#define SH_RTC3_INT_CONFIG_TYPE_MASK             0x0000000000000007

/*   SH_RTC3_INT_CONFIG_AGT                                             */
/*   Description:  Agent, must be 0 for SHub                            */
#define SH_RTC3_INT_CONFIG_AGT_SHFT              3
#define SH_RTC3_INT_CONFIG_AGT_MASK              0x0000000000000008

/*   SH_RTC3_INT_CONFIG_PID                                             */
/*   Description:  Processor ID, same setting as on targeted McKinley  */
#define SH_RTC3_INT_CONFIG_PID_SHFT              4
#define SH_RTC3_INT_CONFIG_PID_MASK              0x00000000000ffff0

/*   SH_RTC3_INT_CONFIG_BASE                                            */
/*   Description:  Optional interrupt vector area, 2MB aligned          */
#define SH_RTC3_INT_CONFIG_BASE_SHFT             21
#define SH_RTC3_INT_CONFIG_BASE_MASK             0x0003ffffffe00000

/*   SH_RTC3_INT_CONFIG_IDX                                             */
/*   Description:  Targeted McKinley interrupt vector                   */
#define SH_RTC3_INT_CONFIG_IDX_SHFT              52
#define SH_RTC3_INT_CONFIG_IDX_MASK              0x0ff0000000000000

/* ==================================================================== */
/*                    Register "SH_RTC3_INT_ENABLE"                     */
/*                SHub RTC 3 Interrupt Enable Registers                 */
/* ==================================================================== */

#define SH1_RTC3_INT_ENABLE                      0x0000000110001700
#define SH2_RTC3_INT_ENABLE                      0x0000000010001700
#define SH_RTC3_INT_ENABLE_MASK                  0x0000000000000001
#define SH_RTC3_INT_ENABLE_INIT                  0x0000000000000000

/*   SH_RTC3_INT_ENABLE_RTC3_ENABLE                                     */
/*   Description:  Enable RTC 3 Interrupt                               */
#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT      0
#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK      0x0000000000000001

/*   SH_EVENT_OCCURRED_RTC1_INT                                         */
/*   Description:  Pending RTC 1 Interrupt                              */
#define SH_EVENT_OCCURRED_RTC1_INT_SHFT          24
#define SH_EVENT_OCCURRED_RTC1_INT_MASK          0x0000000001000000

/*   SH_EVENT_OCCURRED_RTC2_INT                                         */
/*   Description:  Pending RTC 2 Interrupt                              */
#define SH_EVENT_OCCURRED_RTC2_INT_SHFT          25
#define SH_EVENT_OCCURRED_RTC2_INT_MASK          0x0000000002000000

/*   SH_EVENT_OCCURRED_RTC3_INT                                         */
/*   Description:  Pending RTC 3 Interrupt                              */
#define SH_EVENT_OCCURRED_RTC3_INT_SHFT          26
#define SH_EVENT_OCCURRED_RTC3_INT_MASK          0x0000000004000000

/* ==================================================================== */
/*                        Register "SH_INT_CMPB"                        */
/*                  RTC Compare Value for Processor B                   */
/* ==================================================================== */

#define SH1_INT_CMPB                             0x00000001101b0080
#define SH2_INT_CMPB                             0x00000000101b0080
#define SH_INT_CMPB_MASK                         0x007fffffffffffff
#define SH_INT_CMPB_INIT                         0x0000000000000000

/*   SH_INT_CMPB_REAL_TIME_CMPB                                         */
/*   Description:  Real Time Clock Compare                              */
#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT          0
#define SH_INT_CMPB_REAL_TIME_CMPB_MASK          0x007fffffffffffff

/* ==================================================================== */
/*                        Register "SH_INT_CMPC"                        */
/*                  RTC Compare Value for Processor C                   */
/* ==================================================================== */

#define SH1_INT_CMPC                             0x00000001101b0100
#define SH2_INT_CMPC                             0x00000000101b0100
#define SH_INT_CMPC_MASK                         0x007fffffffffffff
#define SH_INT_CMPC_INIT                         0x0000000000000000

/*   SH_INT_CMPC_REAL_TIME_CMPC                                         */
/*   Description:  Real Time Clock Compare                              */
#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT          0
#define SH_INT_CMPC_REAL_TIME_CMPC_MASK          0x007fffffffffffff

/* ==================================================================== */
/*                        Register "SH_INT_CMPD"                        */
/*                  RTC Compare Value for Processor D                   */
/* ==================================================================== */

#define SH1_INT_CMPD                             0x00000001101b0180
#define SH2_INT_CMPD                             0x00000000101b0180
#define SH_INT_CMPD_MASK                         0x007fffffffffffff
#define SH_INT_CMPD_INIT                         0x0000000000000000

/*   SH_INT_CMPD_REAL_TIME_CMPD                                         */
/*   Description:  Real Time Clock Compare                              */
#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT          0
#define SH_INT_CMPD_REAL_TIME_CMPD_MASK          0x007fffffffffffff


/* ==================================================================== */
/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
/* and SHUB2 that it makes sense to define a geberic name for the MMR.  */
/* It is acceptible to use (for example) SH_IPI_INT to reference the    */
/* the IPI MMR. The value of SH_IPI_INT is determined at runtime based  */
/* on the type of the SHUB. Do not use these #defines in performance    */
/* critical code  or loops - there is a small performance penalty.      */
/* ==================================================================== */
#define shubmmr(a,b) 		(is_shub2() ? a##2_##b : a##1_##b)

#define SH_REAL_JUNK_BUS_LED0	shubmmr(SH, REAL_JUNK_BUS_LED0)
#define SH_IPI_INT		shubmmr(SH, IPI_INT)
#define SH_EVENT_OCCURRED	shubmmr(SH, EVENT_OCCURRED)
#define SH_EVENT_OCCURRED_ALIAS	shubmmr(SH, EVENT_OCCURRED_ALIAS)
#define SH_RTC			shubmmr(SH, RTC)
#define SH_RTC1_INT_CONFIG	shubmmr(SH, RTC1_INT_CONFIG)
#define SH_RTC1_INT_ENABLE	shubmmr(SH, RTC1_INT_ENABLE)
#define SH_RTC2_INT_CONFIG	shubmmr(SH, RTC2_INT_CONFIG)
#define SH_RTC2_INT_ENABLE	shubmmr(SH, RTC2_INT_ENABLE)
#define SH_RTC3_INT_CONFIG	shubmmr(SH, RTC3_INT_CONFIG)
#define SH_RTC3_INT_ENABLE	shubmmr(SH, RTC3_INT_ENABLE)
#define SH_INT_CMPB		shubmmr(SH, INT_CMPB)
#define SH_INT_CMPC		shubmmr(SH, INT_CMPC)
#define SH_INT_CMPD		shubmmr(SH, INT_CMPD)

#endif /* _ASM_IA64_SN_SHUB_MMR_H */