test.map.rpt

Altera-jtag0

Analysis & Synthesis report for test
Thu Oct 09 21:37:34 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |test|nios:inst|sdram:the_sdram|m_next
  9. State Machine - |test|nios:inst|sdram:the_sdram|m_state
 10. State Machine - |test|nios:inst|sdram:the_sdram|i_next
 11. State Machine - |test|nios:inst|sdram:the_sdram|i_state
 12. State Machine - |test|nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize
 13. Registers Protected by Synthesis
 14. Registers Removed During Synthesis
 15. Removed Registers Triggering Further Register Optimizations
 16. General Register Statistics
 17. Inverted Register Statistics
 18. Multiplexer Restructuring Statistics (Restructuring Performed)
 19. Source assignments for nios:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_ig22:auto_generated
 20. Source assignments for nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_t072:auto_generated
 21. Source assignments for nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated
 22. Source assignments for nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1
 23. Source assignments for nios:inst|jtag_uart:the_jtag_uart
 24. Source assignments for nios:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2
 25. Source assignments for nios:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2
 26. Source assignments for nios:inst|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram|altsyncram_3jb1:auto_generated
 27. Source assignments for nios:inst|sdram:the_sdram
 28. Source assignments for nios:inst|nios_reset_clk_domain_synch_module:nios_reset_clk_domain_synch
 29. Source assignments for sld_hub:sld_hub_inst
 30. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 31. Parameter Settings for User Entity Instance: pll:inst1|altpll:altpll_component
 32. Parameter Settings for User Entity Instance: nios:inst|cpu:the_cpu|cpu_rf_module:cpu_rf
 33. Parameter Settings for User Entity Instance: nios:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram
 34. Parameter Settings for User Entity Instance: nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component
 35. Parameter Settings for User Entity Instance: nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 36. Parameter Settings for User Entity Instance: nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component
 37. Parameter Settings for User Entity Instance: nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 38. Parameter Settings for User Entity Instance: nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1
 39. Parameter Settings for User Entity Instance: nios:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo
 40. Parameter Settings for User Entity Instance: nios:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo
 41. Parameter Settings for User Entity Instance: nios:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic
 42. Parameter Settings for User Entity Instance: nios:inst|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram
 43. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 44. scfifo Parameter Settings by Entity Instance
 45. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of