test.hier_info

Altera-jtag0

cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata~226.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata~225.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata~224.IN0
cpu_data_master_write => pre_dbs_count_enable~4.IN0
cpu_data_master_write => pre_dbs_count_enable~1.IN0
cpu_data_master_write => last_dbs_term_and_run~0.IN0
cpu_data_master_write => r_1~15.IN0
cpu_data_master_write => r_1~8.IN0
cpu_data_master_write => r_0~38.IN0
cpu_data_master_write => r_0~35.IN0
cpu_data_master_write => r_0~26.IN1
cpu_data_master_write => r_0~7.IN0
cpu_data_master_write => r_0~6.IN0
cpu_data_master_write => r_0~34.IN0
cpu_data_master_write => r_1~6.IN0
cpu_data_master_write => r_1~14.IN0
cpu_data_master_writedata[0] => cpu_data_master_dbs_write_16~15.DATAA
cpu_data_master_writedata[1] => cpu_data_master_dbs_write_16~14.DATAA
cpu_data_master_writedata[2] => cpu_data_master_dbs_write_16~13.DATAA
cpu_data_master_writedata[3] => cpu_data_master_dbs_write_16~12.DATAA
cpu_data_master_writedata[4] => cpu_data_master_dbs_write_16~11.DATAA
cpu_data_master_writedata[5] => cpu_data_master_dbs_write_16~10.DATAA
cpu_data_master_writedata[6] => cpu_data_master_dbs_write_16~9.DATAA
cpu_data_master_writedata[7] => cpu_data_master_dbs_write_16~8.DATAA
cpu_data_master_writedata[8] => cpu_data_master_dbs_write_16~7.DATAA
cpu_data_master_writedata[9] => cpu_data_master_dbs_write_16~6.DATAA
cpu_data_master_writedata[10] => cpu_data_master_dbs_write_16~5.DATAA
cpu_data_master_writedata[11] => cpu_data_master_dbs_write_16~4.DATAA
cpu_data_master_writedata[12] => cpu_data_master_dbs_write_16~3.DATAA
cpu_data_master_writedata[13] => cpu_data_master_dbs_write_16~2.DATAA
cpu_data_master_writedata[14] => cpu_data_master_dbs_write_16~1.DATAA
cpu_data_master_writedata[15] => cpu_data_master_dbs_write_16~0.DATAA
cpu_data_master_writedata[16] => cpu_data_master_dbs_write_16~15.DATAB
cpu_data_master_writedata[17] => cpu_data_master_dbs_write_16~14.DATAB
cpu_data_master_writedata[18] => cpu_data_master_dbs_write_16~13.DATAB
cpu_data_master_writedata[19] => cpu_data_master_dbs_write_16~12.DATAB
cpu_data_master_writedata[20] => cpu_data_master_dbs_write_16~11.DATAB
cpu_data_master_writedata[21] => cpu_data_master_dbs_write_16~10.DATAB
cpu_data_master_writedata[22] => cpu_data_master_dbs_write_16~9.DATAB
cpu_data_master_writedata[23] => cpu_data_master_dbs_write_16~8.DATAB
cpu_data_master_writedata[24] => cpu_data_master_dbs_write_16~7.DATAB
cpu_data_master_writedata[25] => cpu_data_master_dbs_write_16~6.DATAB
cpu_data_master_writedata[26] => cpu_data_master_dbs_write_16~5.DATAB
cpu_data_master_writedata[27] => cpu_data_master_dbs_write_16~4.DATAB
cpu_data_master_writedata[28] => cpu_data_master_dbs_write_16~3.DATAB
cpu_data_master_writedata[29] => cpu_data_master_dbs_write_16~2.DATAB
cpu_data_master_writedata[30] => cpu_data_master_dbs_write_16~1.DATAB
cpu_data_master_writedata[31] => cpu_data_master_dbs_write_16~0.DATAB
cpu_jtag_debug_module_readdata_from_sa[0] => cpu_data_master_readdata~0.IN1
cpu_jtag_debug_module_readdata_from_sa[1] => cpu_data_master_readdata~1.IN1
cpu_jtag_debug_module_readdata_from_sa[2] => cpu_data_master_readdata~2.IN1
cpu_jtag_debug_module_readdata_from_sa[3] => cpu_data_master_readdata~3.IN1
cpu_jtag_debug_module_readdata_from_sa[4] => cpu_data_master_readdata~4.IN1
cpu_jtag_debug_module_readdata_from_sa[5] => cpu_data_master_readdata~5.IN1
cpu_jtag_debug_module_readdata_from_sa[6] => cpu_data_master_readdata~6.IN1
cpu_jtag_debug_module_readdata_from_sa[7] => cpu_data_master_readdata~7.IN1
cpu_jtag_debug_module_readdata_from_sa[8] => cpu_data_master_readdata~8.IN1
cpu_jtag_debug_module_readdata_from_sa[9] => cpu_data_master_readdata~9.IN1
cpu_jtag_debug_module_readdata_from_sa[10] => cpu_data_master_readdata~10.IN1
cpu_jtag_debug_module_readdata_from_sa[11] => cpu_data_master_readdata~11.IN1
cpu_jtag_debug_module_readdata_from_sa[12] => cpu_data_master_readdata~12.IN1
cpu_jtag_debug_module_readdata_from_sa[13] => cpu_data_master_readdata~13.IN1
cpu_jtag_debug_module_readdata_from_sa[14] => cpu_data_master_readdata~14.IN1
cpu_jtag_debug_module_readdata_from_sa[15] => cpu_data_master_readdata~15.IN1
cpu_jtag_debug_module_readdata_from_sa[16] => cpu_data_master_readdata~16.IN1
cpu_jtag_debug_module_readdata_from_sa[17] => cpu_data_master_readdata~17.IN1
cpu_jtag_debug_module_readdata_from_sa[18] => cpu_data_master_readdata~18.IN1
cpu_jtag_debug_module_readdata_from_sa[19] => cpu_data_master_readdata~19.IN1
cpu_jtag_debug_module_readdata_from_sa[20] => cpu_data_master_readdata~20.IN1
cpu_jtag_debug_module_readdata_from_sa[21] => cpu_data_master_readdata~21.IN1
cpu_jtag_debug_module_readdata_from_sa[22] => cpu_data_master_readdata~22.IN1
cpu_jtag_debug_module_readdata_from_sa[23] => cpu_data_master_readdata~23.IN1
cpu_jtag_debug_module_readdata_from_sa[24] => cpu_data_master_readdata~24.IN1
cpu_jtag_debug_module_readdata_from_sa[25] => cpu_data_master_readdata~25.IN1
cpu_jtag_debug_module_readdata_from_sa[26] => cpu_data_master_readdata~26.IN1
cpu_jtag_debug_module_readdata_from_sa[27] => cpu_data_master_readdata~27.IN1
cpu_jtag_debug_module_readdata_from_sa[28] => cpu_data_master_readdata~28.IN1
cpu_jtag_debug_module_readdata_from_sa[29] => cpu_data_master_readdata~29.IN1
cpu_jtag_debug_module_readdata_from_sa[30] => cpu_data_master_readdata~30.IN1
cpu_jtag_debug_module_readdata_from_sa[31] => cpu_data_master_readdata~31.IN1
d1_cpu_jtag_debug_module_end_xfer => ~NO_FANOUT~
d1_jtag_uart_avalon_jtag_slave_end_xfer => ~NO_FANOUT~
d1_onchip_mem_s1_end_xfer => ~NO_FANOUT~
d1_pio_s1_end_xfer => ~NO_FANOUT~
d1_sdram_s1_end_xfer => ~NO_FANOUT~
d1_sysid_control_slave_end_xfer => ~NO_FANOUT~
jtag_uart_avalon_jtag_slave_irq_from_sa => cpu_data_master_irq[0].DATAIN
jtag_uart_avalon_jtag_slave_readdata_from_sa[0] => p1_registered_cpu_data_master_readdata~0.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[1] => p1_registered_cpu_data_master_readdata~1.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[2] => p1_registered_cpu_data_master_readdata~2.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[3] => p1_registered_cpu_data_master_readdata~3.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[4] => p1_registered_cpu_data_master_readdata~4.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[5] => p1_registered_cpu_data_master_readdata~5.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[6] => p1_registered_cpu_data_master_readdata~6.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[7] => p1_registered_cpu_data_master_readdata~7.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[8] => p1_registered_cpu_data_master_readdata~8.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[9] => p1_registered_cpu_data_master_readdata~9.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[10] => p1_registered_cpu_data_master_readdata~10.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[11] => p1_registered_cpu_data_master_readdata~11.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[12] => p1_registered_cpu_data_master_readdata~12.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[13] => p1_registered_cpu_data_master_readdata~13.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[14] => p1_registered_cpu_data_master_readdata~14.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[15] => p1_registered_cpu_data_master_readdata~15.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[16] => p1_registered_cpu_data_master_readdata~16.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[17] => p1_registered_cpu_data_master_readdata~17.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[18] => p1_registered_cpu_data_master_readdata~18.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[19] => p1_registered_cpu_data_master_readdata~19.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[20] => p1_registered_cpu_data_master_readdata~20.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[21] => p1_registered_cpu_data_master_readdata~21.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[22] => p1_registered_cpu_data_master_readdata~22.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[23] => p1_registered_cpu_data_master_readdata~23.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[24] => p1_registered_cpu_data_master_readdata~24.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[25] => p1_registered_cpu_data_master_readdata~25.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[26] => p1_registered_cpu_data_master_readdata~26.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[27] => p1_registered_cpu_data_master_readdata~27.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[28] => p1_registered_cpu_data_master_readdata~28.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[29] => p1_registered_cpu_data_master_readdata~29.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[30] => p1_registered_cpu_data_master_readdata~30.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[31] => p1_registered_cpu_data_master_readdata~31.IN1
jtag_uart_avalon_jtag_slave_waitrequest_from_sa => r_0~13.IN1
onchip_mem_s1_readdata_from_sa[0] => cpu_data_master_readdata~96.IN1
onchip_mem_s1_readdata_from_sa[1] => cpu_data_master_readdata~97.IN1
onchip_mem_s1_readdata_from_sa[2] => cpu_data_master_readdata~98.IN1
onchip_mem_s1_readdata_from_sa[3] => cpu_data_master_readdata~99.IN1
onchip_mem_s1_readdata_from_sa[4] => cpu_data_master_readdata~100.IN1
onchip_mem_s1_readdata_from_sa[5] => cpu_data_master_readdata~101.IN1
onchip_mem_s1_readdata_from_sa[6] => cpu_data_master_readdata~102.IN1
onchip_mem_s1_readdata_from_sa[7] => cpu_data_master_readdata~103.IN1
onchip_mem_s1_readdata_from_sa[8] => cpu_data_master_readdata~104.IN1
onchip_mem_s1_readdata_from_sa[9] => cpu_data_master_readdata~105.IN1
onchip_mem_s1_readdata_from_sa[10] => cpu_data_master_readdata~106.IN1
onchip_mem_s1_readdata_from_sa[11] => cpu_data_master_readdata~107.IN1
onchip_mem_s1_readdata_from_sa[12] => cpu_data_master_readdata~108.IN1
onchip_mem_s1_readdata_from_sa[13] => cpu_data_master_readdata~109.IN1
onchip_mem_s1_readdata_from_sa[14] => cpu_data_master_readdata~110.IN1
onchip_mem_s1_readdata_from_sa[15] => cpu_data_master_readdata~111.IN1
onchip_mem_s1_readdata_from_sa[16] => cpu_data_master_readdata~112.IN1
onchip_mem_s1_readdata_from_sa[17] => cpu_data_master_readdata~113.IN1
onchip_mem_s1_readdata_from_sa[18] => cpu_data_master_readdata~114.IN1
onchip_mem_s1_readdata_from_sa[19] => cpu_data_master_readdata~115.IN1
onchip_mem_s1_readdata_from_sa[20] => cpu_data_master_readdata~116.IN1
onchip_mem_s1_readdata_from_sa[21] => cpu_data_master_readdata~117.IN1
onchip_mem_s1_readdata_from_sa[22] => cpu_data_master_readdata~118.IN1
onchip_mem_s1_readdata_from_sa[23] => cpu_data_master_readdata~119.IN1
onchip_mem_s1_readdata_from_sa[24] => cpu_data_master_readdata~120.IN1
onchip_mem_s1_readdata_from_sa[25] => cpu_data_master_readdata~121.IN1
onchip_mem_s1_readdata_from_sa[26] => cpu_data_master_readdata~122.IN1
onchip_mem_s1_readdata_from_sa[27] => cpu_data_master_readdata~123.IN1
onchip_mem_s1_readdata_from_sa[28] => cpu_data_master_readdata~124.IN1
onchip_mem_s1_readdata_from_sa[29] => cpu_data_master_readdata~125.IN1
onchip_mem_s1_readdata_from_sa[30] => cpu_data_master_readdata~126.IN1
onchip_mem_s1_readdata_from_sa[31] => cpu_data_master_readdata~127.IN1
registered_cpu_data_master_read_data_valid_onchip_mem_s1 => r_0~22.IN1
registered_cpu_data_master_read_data_valid_onchip_mem_s1 => r_0~16.IN1
reset_n => dbs_16_reg_segment_0[0].ACLR
reset_n => dbs_16_reg_segment_0[1].ACLR
reset_n => dbs_16_reg_segment_0[2].ACLR
reset_n => dbs_16_reg_segment_0[3].ACLR
reset_n => dbs_16_reg_segment_0[4].ACLR
reset_n => dbs_16_reg_segment_0[5].ACLR
reset_n => dbs_16_reg_segment_0[6].ACLR
reset_n => dbs_16_reg_segment_0[7].ACLR
reset_n => dbs_16_reg_segment_0[8].ACLR
reset_n => dbs_16_reg_segment_0[9].ACLR
reset_n => dbs_16_reg_segment_0[10].ACLR
reset_n => dbs_16_reg_segment_0[11].ACLR
reset_n => dbs_16_reg_segment_0[12].ACLR
reset_n => dbs_16_reg_segment_0[13].ACLR
reset_n => dbs_16_reg_segment_0[14].ACLR
reset_n => dbs_16_reg_segment_0[15].ACLR
reset_n => cpu_data_master_dbs_address[0]~reg0.ACLR
reset_n => cpu_data_master_dbs_address[1]~reg0.ACLR
reset_n => cpu_data_master_no_byte_enables_and_last_term~reg0.ACLR
reset_n => cpu_data_master_waitrequest~reg0.PRESET
reset_n => registered_cpu_data_master_readdata[31].ACLR
reset_n => registered_cpu_data_master_readdata[30].ACLR
reset_n => registered_cpu_data_master_readdata[29].ACLR
reset_n => registered_cpu_data_master_readdata[28].ACLR
reset_n => registered_cpu_data_master_readdata[27].ACLR
reset_n => registered_cpu_data_master_readdata[26].ACLR
reset_n => registered_cpu_data_master_readdata[25].ACLR
reset_n => registered_cpu_data_master_readdata[24].ACLR
reset_n => registered_cpu_data_master_readdata[23].ACLR
reset_n => registered_cpu_data_master_readdata[22].ACLR
reset_n => registered_cpu_data_master_readdata[21].ACLR
reset_n => registered_cpu_data_master_readdata[20].ACLR
reset_n => registered_cpu_data_master_readdata[19].ACLR
reset_n => registered_cpu_data_master_rea