test.hier_info

Altera-jtag0

|test
clk <= pll:inst1.c0
sysclk => pll:inst1.inclk0
sysclk => nios:inst.clk
cke <= nios:inst.zs_cke_from_the_sdram
reset => nios:inst.reset_n
dq[0] <= nios:inst.zs_dq_to_and_from_the_sdram[0]
dq[1] <= nios:inst.zs_dq_to_and_from_the_sdram[1]
dq[2] <= nios:inst.zs_dq_to_and_from_the_sdram[2]
dq[3] <= nios:inst.zs_dq_to_and_from_the_sdram[3]
dq[4] <= nios:inst.zs_dq_to_and_from_the_sdram[4]
dq[5] <= nios:inst.zs_dq_to_and_from_the_sdram[5]
dq[6] <= nios:inst.zs_dq_to_and_from_the_sdram[6]
dq[7] <= nios:inst.zs_dq_to_and_from_the_sdram[7]
dq[8] <= nios:inst.zs_dq_to_and_from_the_sdram[8]
dq[9] <= nios:inst.zs_dq_to_and_from_the_sdram[9]
dq[10] <= nios:inst.zs_dq_to_and_from_the_sdram[10]
dq[11] <= nios:inst.zs_dq_to_and_from_the_sdram[11]
dq[12] <= nios:inst.zs_dq_to_and_from_the_sdram[12]
dq[13] <= nios:inst.zs_dq_to_and_from_the_sdram[13]
dq[14] <= nios:inst.zs_dq_to_and_from_the_sdram[14]
dq[15] <= nios:inst.zs_dq_to_and_from_the_sdram[15]
cs_n <= nios:inst.zs_cs_n_from_the_sdram
ras <= nios:inst.zs_ras_n_from_the_sdram
we <= nios:inst.zs_we_n_from_the_sdram
cas_n <= nios:inst.zs_cas_n_from_the_sdram
add[0] <= nios:inst.zs_addr_from_the_sdram[0]
add[1] <= nios:inst.zs_addr_from_the_sdram[1]
add[2] <= nios:inst.zs_addr_from_the_sdram[2]
add[3] <= nios:inst.zs_addr_from_the_sdram[3]
add[4] <= nios:inst.zs_addr_from_the_sdram[4]
add[5] <= nios:inst.zs_addr_from_the_sdram[5]
add[6] <= nios:inst.zs_addr_from_the_sdram[6]
add[7] <= nios:inst.zs_addr_from_the_sdram[7]
add[8] <= nios:inst.zs_addr_from_the_sdram[8]
add[9] <= nios:inst.zs_addr_from_the_sdram[9]
add[10] <= nios:inst.zs_addr_from_the_sdram[10]
add[11] <= nios:inst.zs_addr_from_the_sdram[11]
ba[0] <= nios:inst.zs_ba_from_the_sdram[0]
ba[1] <= nios:inst.zs_ba_from_the_sdram[1]
dqm[0] <= nios:inst.zs_dqm_from_the_sdram[0]
dqm[1] <= nios:inst.zs_dqm_from_the_sdram[1]
pio[0] <= nios:inst.out_port_from_the_pio[0]
pio[1] <= nios:inst.out_port_from_the_pio[1]


|test|pll:inst1
inclk0 => sub_wire3[0].IN1
c0 <= altpll:altpll_component.clk


|test|pll:inst1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <= <GND>
clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= <GND>
clk[2] <= <GND>
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>


|test|nios:inst
clk => clk~0.IN15
reset_n => reset_n_sources~0.IN1
out_port_from_the_pio[0] <= pio:the_pio.out_port
out_port_from_the_pio[1] <= pio:the_pio.out_port
zs_addr_from_the_sdram[0] <= sdram:the_sdram.zs_addr
zs_addr_from_the_sdram[1] <= sdram:the_sdram.zs_addr
zs_addr_from_the_sdram[2] <= sdram:the_sdram.zs_addr
zs_addr_from_the_sdram[3] <= sdram:the_sdram.zs_addr
zs_addr_from_the_sdram[4] <= sdram:the_sdram.zs_addr
zs_addr_from_the_sdram[5] <= sdram:the_sdram.zs_addr
zs_addr_from_the_sdram[6] <= sdram:the_sdram.zs_addr
zs_addr_from_the_sdram[7] <= sdram:the_sdram.zs_addr
zs_addr_from_the_sdram[8] <= sdram:the_sdram.zs_addr
zs_addr_from_the_sdram[9] <= sdram:the_sdram.zs_addr
zs_addr_from_the_sdram[10] <= sdram:the_sdram.zs_addr
zs_addr_from_the_sdram[11] <= sdram:the_sdram.zs_addr
zs_ba_from_the_sdram[0] <= sdram:the_sdram.zs_ba
zs_ba_from_the_sdram[1] <= sdram:the_sdram.zs_ba
zs_cas_n_from_the_sdram <= sdram:the_sdram.zs_cas_n
zs_cke_from_the_sdram <= sdram:the_sdram.zs_cke
zs_cs_n_from_the_sdram <= sdram:the_sdram.zs_cs_n
zs_dq_to_and_from_the_sdram[0] <= sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[1] <= sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[2] <= sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[3] <= sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[4] <= sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[5] <= sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[6] <= sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[7] <= sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[8] <= sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[9] <= sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[10] <= sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[11] <= sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[12] <= sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[13] <= sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[14] <= sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[15] <= sdram:the_sdram.zs_dq
zs_dqm_from_the_sdram[0] <= sdram:the_sdram.zs_dqm
zs_dqm_from_the_sdram[1] <= sdram:the_sdram.zs_dqm
zs_ras_n_from_the_sdram <= sdram:the_sdram.zs_ras_n
zs_we_n_from_the_sdram <= sdram:the_sdram.zs_we_n


|test|nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module
clk => d1_reasons_to_wait.CLK
clk => cpu_jtag_debug_module_arb_share_counter[1].CLK
clk => cpu_jtag_debug_module_arb_share_counter[0].CLK
clk => cpu_jtag_debug_module_slavearbiterlockenable.CLK
clk => last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module.CLK
clk => last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module.CLK
clk => cpu_jtag_debug_module_saved_chosen_master_vector[1].CLK
clk => cpu_jtag_debug_module_saved_chosen_master_vector[0].CLK
clk => cpu_jtag_debug_module_arb_addend[1].CLK
clk => cpu_jtag_debug_module_arb_addend[0].CLK
clk => cpu_jtag_debug_module_reg_firsttransfer.CLK
clk => d1_cpu_jtag_debug_module_end_xfer~reg0.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => cpu_jtag_debug_module_address~8.DATAB
cpu_data_master_address_to_slave[3] => cpu_jtag_debug_module_address~7.DATAB
cpu_data_master_address_to_slave[4] => cpu_jtag_debug_module_address~6.DATAB
cpu_data_master_address_to_slave[5] => cpu_jtag_debug_module_address~5.DATAB
cpu_data_master_address_to_slave[6] => cpu_jtag_debug_module_address~4.DATAB
cpu_data_master_address_to_slave[7] => cpu_jtag_debug_module_address~3.DATAB
cpu_data_master_address_to_slave[8] => cpu_jtag_debug_module_address~2.DATAB
cpu_data_master_address_to_slave[9] => cpu_jtag_debug_module_address~1.DATAB
cpu_data_master_address_to_slave[10] => cpu_jtag_debug_module_address~0.DATAB
cpu_data_master_address_to_slave[11] => Equal0.IN35
cpu_data_master_address_to_slave[12] => Equal0.IN10
cpu_data_master_address_to_slave[13] => Equal0.IN9
cpu_data_master_address_to_slave[14] => Equal0.IN34
cpu_data_master_address_to_slave[15] => Equal0.IN8
cpu_data_master_address_to_slave[16] => Equal0.IN7
cpu_data_master_address_to_slave[17] => Equal0.IN6
cpu_data_master_address_to_slave[18] => Equal0.IN5
cpu_data_master_address_to_slave[19] => Equal0.IN4
cpu_data_master_address_to_slave[20] => Equal0.IN3
cpu_data_master_address_to_slave[21] => Equal0.IN2
cpu_data_master_address_to_slave[22] => Equal0.IN1