prev_cmp_test.map.qmsg

Altera-jtag0

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rdv_fifo_for_cpu_data_master_to_sdram_s1_module nios:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1 " "Info: Elaborating entity \"rdv_fifo_for_cpu_data_master_to_sdram_s1_module\" for hierarchy \"nios:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\"" {  } { { "nios.v" "rdv_fifo_for_cpu_data_master_to_sdram_s1" { Text "C:/EP2C5/www_sdram/nios.v" 2594 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module nios:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1 " "Info: Elaborating entity \"rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module\" for hierarchy \"nios:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\"" {  } { { "nios.v" "rdv_fifo_for_cpu_instruction_master_to_sdram_s1" { Text "C:/EP2C5/www_sdram/nios.v" 2632 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "sdram.v 2 2 " "Warning: Using design file sdram.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_input_efifo_module " "Info: Found entity 1: sdram_input_efifo_module" {  } { { "sdram.v" "" { Text "C:/EP2C5/www_sdram/sdram.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 sdram " "Info: Found entity 2: sdram" {  } { { "sdram.v" "" { Text "C:/EP2C5/www_sdram/sdram.v" 155 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram nios:inst\|sdram:the_sdram " "Info: Elaborating entity \"sdram\" for hierarchy \"nios:inst\|sdram:the_sdram\"" {  } { { "nios.v" "the_sdram" { Text "C:/EP2C5/www_sdram/nios.v" 3544 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_2091_UNCONVERTED" "sdram.v(352) " "Warning (10766): Verilog HDL warning at sdram.v(352): ignoring full_case attribute on case statement with explicit default" {  } { { "sdram.v" "" { Text "C:/EP2C5/www_sdram/sdram.v" 352 0 0 } }  } 0 10766 "Verilog HDL warning at %1!s!: ignoring full_case attribute on case statement with explicit default" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_input_efifo_module nios:inst\|sdram:the_sdram\|sdram_input_efifo_module:the_sdram_input_efifo_module " "Info: Elaborating entity \"sdram_input_efifo_module\" for hierarchy \"nios:inst\|sdram:the_sdram\|sdram_input_efifo_module:the_sdram_input_efifo_module\"" {  } { { "sdram.v" "the_sdram_input_efifo_module" { Text "C:/EP2C5/www_sdram/sdram.v" 293 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_2091_UNCONVERTED" "sdram.v(67) " "Warning (10766): Verilog HDL warning at sdram.v(67): ignoring full_case attribute on case statement with explicit default" {  } { { "sdram.v" "" { Text "C:/EP2C5/www_sdram/sdram.v" 67 0 0 } }  } 0 10766 "Verilog HDL warning at %1!s!: ignoring full_case attribute on case statement with explicit default" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_2091_UNCONVERTED" "sdram.v(93) " "Warning (10766): Verilog HDL warning at sdram.v(93): ignoring full_case attribute on case statement with explicit default" {  } { { "sdram.v" "" { Text "C:/EP2C5/www_sdram/sdram.v" 93 0 0 } }  } 0 10766 "Verilog HDL warning at %1!s!: ignoring full_case attribute on case statement with explicit default" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_2091_UNCONVERTED" "sdram.v(129) " "Warning (10766): Verilog HDL warning at sdram.v(129): ignoring full_case attribute on case statement with explicit default" {  } { { "sdram.v" "" { Text "C:/EP2C5/www_sdram/sdram.v" 129 0 0 } }  } 0 10766 "Verilog HDL warning at %1!s!: ignoring full_case attribute on case statement with explicit default" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sysid_control_slave_arbitrator nios:inst\|sysid_control_slave_arbitrator:the_sysid_control_slave " "Info: Elaborating entity \"sysid_control_slave_arbitrator\" for hierarchy \"nios:inst\|sysid_control_slave_arbitrator:the_sysid_control_slave\"" {  } { { "nios.v" "the_sysid_control_slave" { Text "C:/EP2C5/www_sdram/nios.v" 3561 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "sysid.v 1 1 " "Warning: Using design file sysid.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sysid " "Info: Found entity 1: sysid" {  } { { "sysid.v" "" { Text "C:/EP2C5/www_sdram/sysid.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sysid nios:inst\|sysid:the_sysid " "Info: Elaborating entity \"sysid\" for hierarchy \"nios:inst\|sysid:the_sysid\"" {  } { { "nios.v" "the_sysid" { Text "C:/EP2C5/www_sdram/nios.v" 3567 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_reset_clk_domain_synch_module nios:inst\|nios_reset_clk_domain_synch_module:nios_reset_clk_domain_synch " "Info: Elaborating entity \"nios_reset_clk_domain_synch_module\" for hierarchy \"nios:inst\|nios_reset_clk_domain_synch_module:nios_reset_clk_domain_synch\"" {  } { { "nios.v" "nios_reset_clk_domain_synch" { Text "C:/EP2C5/www_sdram/nios.v" 3576 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "address_b cpu_traceram_lpm_dram_bdp_component 17 7 " "Warning (12020): Port \"address_b\" on the entity instantiation of \"cpu_traceram_lpm_dram_bdp_component\" is connected to a signal of width 17. The formal width of the signal in the module is 7.  Extra bits will be ignored." {  } { { "cpu.v" "cpu_traceram_lpm_dram_bdp_component" { Text "C:/EP2C5/www_sdram/cpu.v" 2807 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "jdo the_cpu_nios2_oci_itrace 38 16 " "Warning (12020): Port \"jdo\" on the entity instantiation of \"the_cpu_nios2_oci_itrace\" is connected to a signal of width 38. The formal width of the signal in the module is 16.  Extra bits will be ignored." {  } { { "cpu.v" "the_cpu_nios2_oci_itrace" { Text "C:/EP2C5/www_sdram/cpu.v" 3188 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "dbrk cpu_nios2_oci_dbrk_hit3_match_single 78 71 " "Warning (12020): Port \"dbrk\" on the entity instantiation of \"cpu_nios2_oci_dbrk_hit3_match_single\" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored." {  } { { "cpu.v" "cpu_nios2_oci_dbrk_hit3_match_single" { Text "C:/EP2C5/www_sdram/cpu.v" 1505 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "dbrk cpu_nios2_oci_dbrk_hit2_match_single 78 71 " "Warning (12020): Port \"dbrk\" on the entity instantiation of \"cpu_nios2_oci_dbrk_hit2_match_single\" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored." {  } { { "cpu.v" "cpu_nios2_oci_dbrk_hit2_match_single" { Text "C:/EP2C5/www_sdram/cpu.v" 1493 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "dbrka cpu_nios2_oci_dbrk_hit2_match_paired 78 71 " "Warning (12020): Port \"dbrka\" on the entity instantiation of \"cpu_nios2_oci_dbrk_hit2_match_paired\" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored." {  } { { "cpu.v" "cpu_nios2_oci_dbrk_hit2_match_paired" { Text "C:/EP2C5/www_sdram/cpu.v" 1482 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "dbrkb cpu_nios2_oci_dbrk_hit2_match_paired 78 71 " "Warning (12020): Port \"dbrkb\" on the entity instantiation of \"cpu_nios2_oci_dbrk_hit2_match_paired\" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored." {  } { { "cpu.v" "cpu_nios2_oci_dbrk_hit2_match_paired" { Text "C:/EP2C5/www_sdram/cpu.v" 1482 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "dbrk cpu_nios2_oci_dbrk_hit1_match_single 78 71 " "Warning (12020): Port \"dbrk\" on the entity instantiation of \"cpu_nios2_oci_dbrk_hit1_match_single\" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored." {  } { { "cpu.v" "cpu_nios2_oci_dbrk_hit1_match_single" { Text "C:/EP2C5/www_sdram/cpu.v" 1469 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "dbrk cpu_nios2_oci_dbrk_hit0_match_single 78 71 " "Warning (12020): Port \"dbrk\" on the entity instantiation of \"cpu_nios2_oci_dbrk_hit0_match_single\" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored." {  } { { "cpu.v" "cpu_nios2_oci_dbrk_hit0_match_single" { Text "C:/EP2C5/www_sdram/cpu.v" 1457 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "dbrka cpu_nios2_oci_dbrk_hit0_match_paired 78 71 " "Warning (12020): Port \"dbrka\" on the entity instantiation of \"cpu_nios2_oci_dbrk_hit0_match_paired\" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored." {  } { { "cpu.v" "cpu_nios2_oci_dbrk_hit0_match_paired" { Text "C:/EP2C5/www_sdram/cpu.v" 1446 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "dbrkb cpu_nios2_oci_dbrk_hit0_match_paired 78 71 " "Warning (12020): Port \"dbrkb\" on the entity instantiation of \"cpu_nios2_oci_dbrk_hit0_match_paired\" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored." {  } { { "cpu.v" "cpu_nios2_oci_dbrk_hit0_match_paired" { Text "C:/EP2C5/www_sdram/cpu.v" 1446 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "nios:inst\|sdram:the_sdram\|i_addr\[5\] High " "Info: Power-up level of register \"nios:inst\|sdram:the_sdram\|i_addr\[5\]\" is not specified -- using power-up level of High to minimize register" {  } { { "sdram.v" "" { Text "C:/EP2C5/www_sdram/sdram.v" 407 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "nios:inst\|sdram:the_sdram\|i_addr\[5\] data_in VCC " "Warning (14130): Reduced register \"nios:inst\|sdram:the_sdram\|i_addr\[5\]\" with stuck data_in port to stuck value VCC" {  } { { "sdram.v" "" { Text "C:/EP2C5/www_sdram/sdram.v" 407 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}