test.tan.qmsg

Altera-jtag0

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "sysclk register nios:inst\|sdram:the_sdram\|i_cmd\[3\] register nios:inst\|sdram:the_sdram\|i_cmd\[3\] 499 ps " "Info: Minimum slack time is 499 ps for clock \"sysclk\" between source register \"nios:inst\|sdram:the_sdram\|i_cmd\[3\]\" and destination register \"nios:inst\|sdram:the_sdram\|i_cmd\[3\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.501 ns + Shortest register register " "Info: + Shortest register to register delay is 0.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns nios:inst\|sdram:the_sdram\|i_cmd\[3\] 1 REG LCFF_X17_Y10_N27 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y10_N27; Fanout = 2; REG Node = 'nios:inst\|sdram:the_sdram\|i_cmd\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { nios:inst|sdram:the_sdram|i_cmd[3] } "NODE_NAME" } } { "sdram.v" "" { Text "C:/www_sdram/sdram.v" 407 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns nios:inst\|sdram:the_sdram\|Selector0~8 2 COMB LCCOMB_X17_Y10_N26 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X17_Y10_N26; Fanout = 1; COMB Node = 'nios:inst\|sdram:the_sdram\|Selector0~8'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { nios:inst|sdram:the_sdram|i_cmd[3] nios:inst|sdram:the_sdram|Selector0~8 } "NODE_NAME" } } { "sdram.v" "" { Text "C:/www_sdram/sdram.v" 352 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.501 ns nios:inst\|sdram:the_sdram\|i_cmd\[3\] 3 REG LCFF_X17_Y10_N27 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X17_Y10_N27; Fanout = 2; REG Node = 'nios:inst\|sdram:the_sdram\|i_cmd\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { nios:inst|sdram:the_sdram|Selector0~8 nios:inst|sdram:the_sdram|i_cmd[3] } "NODE_NAME" } } { "sdram.v" "" { Text "C:/www_sdram/sdram.v" 407 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.501 ns ( 100.00 % ) " "Info: Total cell delay = 0.501 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { nios:inst|sdram:the_sdram|i_cmd[3] nios:inst|sdram:the_sdram|Selector0~8 nios:inst|sdram:the_sdram|i_cmd[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { nios:inst|sdram:the_sdram|i_cmd[3] {} nios:inst|sdram:the_sdram|Selector0~8 {} nios:inst|sdram:the_sdram|i_cmd[3] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.002 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.002 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination sysclk 50.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"sysclk\" is 50.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source sysclk 50.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"sysclk\" is 50.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sysclk destination 2.793 ns + Longest register " "Info: + Longest clock path from clock \"sysclk\" to destination register is 2.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns sysclk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'sysclk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sysclk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/www_sdram/test.bdf" { { 112 144 312 128 "sysclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns sysclk~clkctrl 2 COMB CLKCTRL_G2 1511 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 1511; COMB Node = 'sysclk~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { sysclk sysclk~clkctrl } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/www_sdram/test.bdf" { { 112 144 312 128 "sysclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.844 ns) + CELL(0.666 ns) 2.793 ns nios:inst\|sdram:the_sdram\|i_cmd\[3\] 3 REG LCFF_X17_Y10_N27 2 " "Info: 3: + IC(0.844 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X17_Y10_N27; Fanout = 2; REG Node = 'nios:inst\|sdram:the_sdram\|i_cmd\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.510 ns" { sysclk~clkctrl nios:inst|sdram:the_sdram|i_cmd[3] } "NODE_NAME" } } { "sdram.v" "" { Text "C:/www_sdram/sdram.v" 407 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.66 % ) " "Info: Total cell delay = 1.806 ns ( 64.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.987 ns ( 35.34 % ) " "Info: Total interconnect delay = 0.987 ns ( 35.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { sysclk sysclk~clkctrl nios:inst|sdram:the_sdram|i_cmd[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|sdram:the_sdram|i_cmd[3] {} } { 0.000ns 0.000ns 0.143ns 0.844ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sysclk source 2.793 ns - Shortest register " "Info: - Shortest clock path from clock \"sysclk\" to source register is 2.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns sysclk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'sysclk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sysclk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/www_sdram/test.bdf" { { 112 144 312 128 "sysclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns sysclk~clkctrl 2 COMB CLKCTRL_G2 1511 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 1511; COMB Node = 'sysclk~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { sysclk sysclk~clkctrl } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/www_sdram/test.bdf" { { 112 144 312 128 "sysclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.844 ns) + CELL(0.666 ns) 2.793 ns nios:inst\|sdram:the_sdram\|i_cmd\[3\] 3 REG LCFF_X17_Y10_N27 2 " "Info: 3: + IC(0.844 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X17_Y10_N27; Fanout = 2; REG Node = 'nios:inst\|sdram:the_sdram\|i_cmd\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.510 ns" { sysclk~clkctrl nios:inst|sdram:the_sdram|i_cmd[3] } "NODE_NAME" } } { "sdram.v" "" { Text "C:/www_sdram/sdram.v" 407 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.66 % ) " "Info: Total cell delay = 1.806 ns ( 64.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.987 ns ( 35.34 % ) " "Info: Total interconnect delay = 0.987 ns ( 35.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { sysclk sysclk~clkctrl nios:inst|sdram:the_sdram|i_cmd[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|sdram:the_sdram|i_cmd[3] {} } { 0.000ns 0.000ns 0.143ns 0.844ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { sysclk sysclk~clkctrl nios:inst|sdram:the_sdram|i_cmd[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|sdram:the_sdram|i_cmd[3] {} } { 0.000ns 0.000ns 0.143ns 0.844ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { sysclk sysclk~clkctrl nios:inst|sdram:the_sdram|i_cmd[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|sdram:the_sdram|i_cmd[3] {} } { 0.000ns 0.000ns 0.143ns 0.844ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "sdram.v" "" { Text "C:/www_sdram/sdram.v" 407 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "sdram.v" "" { Text "C:/www_sdram/sdram.v" 407 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { sysclk sysclk~clkctrl nios:inst|sdram:the_sdram|i_cmd[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|sdram:the_sdram|i_cmd[3] {} } { 0.000ns 0.000ns 0.143ns 0.844ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { sysclk sysclk~clkctrl nios:inst|sdram:the_sdram|i_cmd[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|sdram:the_sdram|i_cmd[3] {} } { 0.000ns 0.000ns 0.143ns 0.844ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { nios:inst|sdram:the_sdram|i_cmd[3] nios:inst|sdram:the_sdram|Selector0~8 nios:inst|sdram:the_sdram|i_cmd[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { nios:inst|sdram:the_sdram|i_cmd[3] {} nios:inst|sdram:the_sdram|Selector0~8 {} nios:inst|sdram:the_sdram|i_cmd[3] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { sysclk sysclk~clkctrl nios:inst|sdram:the_sdram|i_cmd[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|sdram:the_sdram|i_cmd[3] {} } { 0.000ns 0.000ns 0.143ns 0.844ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { sysclk sysclk~clkctrl nios:inst|sdram:the_sdram|i_cmd[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|sdram:the_sdram|i_cmd[3] {} } { 0.000ns 0.000ns 0.143ns 0.844ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|sr\[11\] altera_internal_jtag~SHIFTUSER altera_internal_jtag~TCKUTAP 7.949 ns register " "Info: tsu for register \"nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|sr\[11\]\" (data pin = \"altera_internal_jtag~SHIFTUSER\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 7.949 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.310 ns + Longest pin register " "Info: + Longest pin to register delay is 13.310 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~SHIFTUSER 1 PIN JTAG_X1_Y7_N0 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y7_N0; Fanout = 3; PIN Node = 'altera_internal_jtag~SHIFTUSER'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~SHIFTUSER } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.444 ns) + CELL(0.651 ns) 5.095 ns nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|always2~67 2 COMB LCCOMB_X9_Y6_N16 38 " "Info: 2: + IC(4.444 ns) + CELL(0.651 ns) = 5.095 ns; Loc. = LCCOMB_X9_Y6_N16; Fanout = 38; COMB Node = 'nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|always2~67'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.095 ns" { altera_internal_jtag~SHIFTUSER nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|always2~67 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.649 ns) + CELL(0.206 ns) 6.950 ns nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|sr\[12\]~4010 3 COMB LCCOMB_X12_Y3_N30 23 " "Info: 3: + IC(1.649 ns) + CELL(0.206 ns) = 6.950 ns; Loc. = LCCOMB_X12_Y3_N30; Fanout = 23; COMB Node = 'nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|sr\[12\]~4010'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.855 ns" { nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|always2~67 nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[12]~4010 } "NODE_NAME" } } { "cpu_jtag_debug_module.v" "" { Text "C:/www_sdram/cpu_jtag_debug_module.v" 230 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.887 ns) + CELL(0.651 ns) 10.488 ns nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|sr~4073 4 COMB LCCOMB_X12_Y6_N10 1 " "Info: 4: + IC(2.887 ns) + CELL(0.651 ns) = 10.488 ns; Loc. = LCCOMB_X12_Y6_N10; Fanout = 1; COMB Node = 'nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|sr~4073'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.538 ns" { nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[12]~4010 nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jta