📄 test.tan.qmsg
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{ "Info" "ITAN_NO_REG2REG_EXIST" "pll:inst1\|altpll:altpll_component\|_clk0 " "Info: No valid register-to-register data paths exist for clock \"pll:inst1\|altpll:altpll_component\|_clk0\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "sysclk register nios:inst\|cpu:the_cpu\|F_pc\[18\] register nios:inst\|cpu:the_cpu\|av_ld_byte0_data\[2\] 34.428 ns " "Info: Slack time is 34.428 ns for clock \"sysclk\" between source register \"nios:inst\|cpu:the_cpu\|F_pc\[18\]\" and destination register \"nios:inst\|cpu:the_cpu\|av_ld_byte0_data\[2\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "64.22 MHz 15.572 ns " "Info: Fmax is 64.22 MHz (period= 15.572 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "49.724 ns + Largest register register " "Info: + Largest register to register requirement is 49.724 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "50.000 ns + " "Info: + Setup relationship between source and destination is 50.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 50.000 ns " "Info: + Latch edge is 50.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination sysclk 50.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"sysclk\" is 50.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source sysclk 50.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"sysclk\" is 50.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.012 ns + Largest " "Info: + Largest clock skew is -0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sysclk destination 2.764 ns + Shortest register " "Info: + Shortest clock path from clock \"sysclk\" to destination register is 2.764 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns sysclk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'sysclk'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sysclk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/www_sdram/test.bdf" { { 112 144 312 128 "sysclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns sysclk~clkctrl 2 COMB CLKCTRL_G2 1511 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 1511; COMB Node = 'sysclk~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { sysclk sysclk~clkctrl } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/www_sdram/test.bdf" { { 112 144 312 128 "sysclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.815 ns) + CELL(0.666 ns) 2.764 ns nios:inst\|cpu:the_cpu\|av_ld_byte0_data\[2\] 3 REG LCFF_X17_Y6_N29 1 " "Info: 3: + IC(0.815 ns) + CELL(0.666 ns) = 2.764 ns; Loc. = LCFF_X17_Y6_N29; Fanout = 1; REG Node = 'nios:inst\|cpu:the_cpu\|av_ld_byte0_data\[2\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.481 ns" { sysclk~clkctrl nios:inst|cpu:the_cpu|av_ld_byte0_data[2] } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 4708 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.34 % ) " "Info: Total cell delay = 1.806 ns ( 65.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.958 ns ( 34.66 % ) " "Info: Total interconnect delay = 0.958 ns ( 34.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.764 ns" { sysclk sysclk~clkctrl nios:inst|cpu:the_cpu|av_ld_byte0_data[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.764 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|cpu:the_cpu|av_ld_byte0_data[2] {} } { 0.000ns 0.000ns 0.143ns 0.815ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sysclk source 2.776 ns - Longest register " "Info: - Longest clock path from clock \"sysclk\" to source register is 2.776 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns sysclk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'sysclk'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sysclk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/www_sdram/test.bdf" { { 112 144 312 128 "sysclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns sysclk~clkctrl 2 COMB CLKCTRL_G2 1511 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 1511; COMB Node = 'sysclk~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { sysclk sysclk~clkctrl } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/www_sdram/test.bdf" { { 112 144 312 128 "sysclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.827 ns) + CELL(0.666 ns) 2.776 ns nios:inst\|cpu:the_cpu\|F_pc\[18\] 3 REG LCFF_X26_Y6_N9 4 " "Info: 3: + IC(0.827 ns) + CELL(0.666 ns) = 2.776 ns; Loc. = LCFF_X26_Y6_N9; Fanout = 4; REG Node = 'nios:inst\|cpu:the_cpu\|F_pc\[18\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { sysclk~clkctrl nios:inst|cpu:the_cpu|F_pc[18] } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 4293 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.06 % ) " "Info: Total cell delay = 1.806 ns ( 65.06 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.970 ns ( 34.94 % ) " "Info: Total interconnect delay = 0.970 ns ( 34.94 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.776 ns" { sysclk sysclk~clkctrl nios:inst|cpu:the_cpu|F_pc[18] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.776 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|cpu:the_cpu|F_pc[18] {} } { 0.000ns 0.000ns 0.143ns 0.827ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.764 ns" { sysclk sysclk~clkctrl nios:inst|cpu:the_cpu|av_ld_byte0_data[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.764 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|cpu:the_cpu|av_ld_byte0_data[2] {} } { 0.000ns 0.000ns 0.143ns 0.815ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.776 ns" { sysclk sysclk~clkctrl nios:inst|cpu:the_cpu|F_pc[18] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.776 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|cpu:the_cpu|F_pc[18] {} } { 0.000ns 0.000ns 0.143ns 0.827ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" { } { { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 4293 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" { } { { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 4708 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.764 ns" { sysclk sysclk~clkctrl nios:inst|cpu:the_cpu|av_ld_byte0_data[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.764 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|cpu:the_cpu|av_ld_byte0_data[2] {} } { 0.000ns 0.000ns 0.143ns 0.815ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.776 ns" { sysclk sysclk~clkctrl nios:inst|cpu:the_cpu|F_pc[18] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.776 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|cpu:the_cpu|F_pc[18] {} } { 0.000ns 0.000ns 0.143ns 0.827ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.296 ns - Longest register register " "Info: - Longest register to register delay is 15.296 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns nios:inst\|cpu:the_cpu\|F_pc\[18\] 1 REG LCFF_X26_Y6_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y6_N9; Fanout = 4; REG Node = 'nios:inst\|cpu:the_cpu\|F_pc\[18\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { nios:inst|cpu:the_cpu|F_pc[18] } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 4293 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.962 ns) + CELL(0.202 ns) 3.164 ns nios:inst\|onchip_mem_s1_arbitrator:the_onchip_mem_s1\|cpu_instruction_master_requests_onchip_mem_s1~319 2 COMB LCCOMB_X17_Y9_N22 2 " "Info: 2: + IC(2.962 ns) + CELL(0.202 ns) = 3.164 ns; Loc. = LCCOMB_X17_Y9_N22; Fanout = 2; COMB Node = 'nios:inst\|onchip_mem_s1_arbitrator:the_onchip_mem_s1\|cpu_instruction_master_requests_onchip_mem_s1~319'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.164 ns" { nios:inst|cpu:the_cpu|F_pc[18] nios:inst|onchip_mem_s1_arbitrator:the_onchip_mem_s1|cpu_instruction_master_requests_onchip_mem_s1~319 } "NODE_NAME" } } { "nios.v" "" { Text "C:/www_sdram/nios.v" 1303 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.445 ns) + CELL(0.206 ns) 4.815 ns nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_instruction_master_requests_cpu_jtag_debug_module~249 3 COMB LCCOMB_X21_Y5_N26 23 " "Info: 3: + IC(1.445 ns) + CELL(0.206 ns) = 4.815 ns; Loc. = LCCOMB_X21_Y5_N26; Fanout = 23; COMB Node = 'nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_instruction_master_requests_cpu_jtag_debug_module~249'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.651 ns" { nios:inst|onchip_mem_s1_arbitrator:the_onchip_mem_s1|cpu_instruction_master_requests_onchip_mem_s1~319 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~249 } "NODE_NAME" } } { "nios.v" "" { Text "C:/www_sdram/nios.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.131 ns) + CELL(0.206 ns) 6.152 ns nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_address\[8\]~125 4 COMB LCCOMB_X20_Y7_N28 8 " "Info: 4: + IC(1.131 ns) + CELL(0.206 ns) = 6.152 ns; Loc. = LCCOMB_X20_Y7_N28; Fanout = 8; COMB Node = 'nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_address\[8\]~125'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.337 ns" { nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~249 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[8]~125 } "NODE_NAME" } } { "nios.v" "" { Text "C:/www_sdram/nios.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.510 ns) + CELL(0.206 ns) 7.868 ns nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_address\[5\]~131 5 COMB LCCOMB_X18_Y3_N12 3 " "Info: 5: + IC(1.510 ns) + CELL(0.206 ns) = 7.868 ns; Loc. = LCCOMB_X18_Y3_N12; Fanout = 3; COMB Node = 'nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_address\[5\]~131'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.716 ns" { nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[8]~125 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[5]~131 } "NODE_NAME" } } { "nios.v" "" { Text "C:/www_sdram/nios.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.131 ns) + CELL(0.534 ns) 9.533 ns nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|Equal0~68 6 COMB LCCOMB_X18_Y5_N28 4 " "Info: 6: + IC(1.131 ns) + CELL(0.534 ns) = 9.533 ns; Loc. = LCCOMB_X18_Y5_N28; Fanout = 4; COMB Node = 'nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|Equal0~68'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.665 ns" { nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[5]~131 nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~68 } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 508 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.687 ns) + CELL(0.370 ns) 11.590 ns nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1937 7 COMB LCCOMB_X13_Y7_N20 1 " "Info: 7: + IC(1.687 ns) + CELL(0.370 ns) = 11.590 ns; Loc. = LCCOMB_X13_Y7_N20; Fanout = 1; COMB Node = 'nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1937'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.057 ns" { nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~68 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1937 } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 3884 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.527 ns) + CELL(0.206 ns) 13.323 ns nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1938 8 COMB LCCOMB_X17_Y4_N4 1 " "Info: 8: + IC(1.527 ns) + CELL(0.206 ns) = 13.323 ns; Loc. = LCCOMB_X17_Y4_N4; Fanout = 1; COMB Node = 'nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1938'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.733 ns" { nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1937 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1938 } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 3884 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.102 ns) + CELL(0.206 ns) 14.631 ns nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1939 9 COMB LCCOMB_X17_Y6_N26 1 " "Info: 9: + IC(1.102 ns) + CELL(0.206 ns) = 14.631 ns; Loc. = LCCOMB_X17_Y6_N26; Fanout = 1; COMB Node = 'nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1939'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.308 ns" { nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1938 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1939 } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 3884 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.351 ns) + CELL(0.206 ns) 15.188 ns nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1940 10 COMB LCCOMB_X17_Y6_N28 1 " "Info: 10: + IC(0.351 ns) + CELL(0.206 ns) = 15.188 ns; Loc. = LCCOMB_X17_Y6_N28; Fanout = 1; COMB Node = 'nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1940'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.557 ns" { nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1939 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1940 } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 3884 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 15.296 ns nios:inst\|cpu:the_cpu\|av_ld_byte0_data\[2\] 11 REG LCFF_X17_Y6_N29 1 " "Info: 11: + IC(0.000 ns) + CELL(0.108 ns) = 15.296 ns; Loc. = LCFF_X17_Y6_N29; Fanout = 1; REG Node = 'nios:inst\|cpu:the_cpu\|av_ld_byte0_data\[2\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1940 nios:inst|cpu:the_cpu|av_ld_byte0_data[2] } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 4708 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.450 ns ( 16.02 % ) " "Info: Total cell delay = 2.450 ns ( 16.02 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.846 ns ( 83.98 % ) " "Info: Total interconnect delay = 12.846 ns ( 83.98 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.296 ns" { nios:inst|cpu:the_cpu|F_pc[18] nios:inst|onchip_mem_s1_arbitrator:the_onchip_mem_s1|cpu_instruction_master_requests_onchip_mem_s1~319 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~249 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[8]~125 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[5]~131 nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~68 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1937 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1938 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1939 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1940 nios:inst|cpu:the_cpu|av_ld_byte0_data[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.296 ns" { nios:inst|cpu:the_cpu|F_pc[18] {} nios:inst|onchip_mem_s1_arbitrator:the_onchip_mem_s1|cpu_instruction_master_requests_onchip_mem_s1~319 {} nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~249 {} nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[8]~125 {} nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[5]~131 {} nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~68 {} nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1937 {} nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1938 {} nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1939 {} nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1940 {} nios:inst|cpu:the_cpu|av_ld_byte0_data[2] {} } { 0.000ns 2.962ns 1.445ns 1.131ns 1.510ns 1.131ns 1.687ns 1.527ns 1.102ns 0.351ns 0.000ns } { 0.000ns 0.202ns 0.206ns 0.206ns 0.206ns 0.534ns 0.370ns 0.206ns 0.206ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.764 ns" { sysclk sysclk~clkctrl nios:inst|cpu:the_cpu|av_ld_byte0_data[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.764 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|cpu:the_cpu|av_ld_byte0_data[2] {} } { 0.000ns 0.000ns 0.143ns 0.815ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.776 ns" { sysclk sysclk~clkctrl nios:inst|cpu:the_cpu|F_pc[18] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.776 ns" { sysclk {} sysclk~combout {} sysclk~clkctrl {} nios:inst|cpu:the_cpu|F_pc[18] {} } { 0.000ns 0.000ns 0.143ns 0.827ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.296 ns" { nios:inst|cpu:the_cpu|F_pc[18] nios:inst|onchip_mem_s1_arbitrator:the_onchip_mem_s1|cpu_instruction_master_requests_onchip_mem_s1~319 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~249 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[8]~125 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[5]~131 nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~68 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1937 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1938 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1939 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1940 nios:inst|cpu:the_cpu|av_ld_byte0_data[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.296 ns" { nios:inst|cpu:the_cpu|F_pc[18] {} nios:inst|onchip_mem_s1_arbitrator:the_onchip_mem_s1|cpu_instruction_master_requests_onchip_mem_s1~319 {} nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~249 {} nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[8]~125 {} nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[5]~131 {} nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~68 {} nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1937 {} nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1938 {} nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1939 {} nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1940 {} nios:inst|cpu:the_cpu|av_ld_byte0_data[2] {} } { 0.000ns 2.962ns 1.445ns 1.131ns 1.510ns 1.131ns 1.687ns 1.527ns 1.102ns 0.351ns 0.000ns } { 0.000ns 0.202ns 0.206ns 0.206ns 0.206ns 0.534ns 0.370ns 0.206ns 0.206ns 0.206ns 0.108ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_aoi:auto_generated\|dffe1a\[0\] register sld_hub:sld_hub_inst\|hub_tdo_reg 79.08 MHz 12.646 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 79.08 MHz between source register \"sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_aoi:auto_generated\|dffe1a\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 12.646 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.051 ns + Longest register register " "Info: + Longest register to register delay is 6.051 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_aoi:auto_generated\|dffe1a\[0\] 1 REG LCFF_X7_Y4_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X7_Y4_N5; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_aoi:auto_generated\|dffe1a\[0\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0] } "NODE_NAME" } } { "db/decode_aoi.tdf" "" { Text "C:/www_sdram/db/decode_aoi.tdf" 32 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.228 ns) + CELL(0.650 ns) 1.878 ns sld_hub:sld_hub_inst\|hub_tdo_reg~323 2 COMB LCCOMB_X7_Y5_N24 1 " "Info: 2: + IC(1.228 ns) + CELL(0.650 ns) = 1.878 ns; Loc. = LCCOMB_X7_Y5_N24; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~323'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.878 ns" { sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0] sld_hub:sld_hub_inst|hub_tdo_reg~323 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.483 ns) + CELL(0.623 ns) 3.984 ns sld_hub:sld_hub_inst\|hub_tdo_reg~325 3 COMB LCCOMB_X9_Y6_N20 1 " "Info: 3: + IC(1.483 ns) + CELL(0.623 ns) = 3.984 ns; Loc. = LCCOMB_X9_Y6_N20; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~325'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.106 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~323 sld_hub:sld_hub_inst|hub_tdo_reg~325 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.343 ns) + CELL(0.616 ns) 5.943 ns sld_hub:sld_hub_inst\|hub_tdo_reg~326 4 COMB LCCOMB_X6_Y5_N28 1 " "Info: 4: + IC(1.343 ns) + CELL(0.616 ns) = 5.943 ns; Loc. = LCCOMB_X6_Y5_N28; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~326'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.959 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~325 sld_hub:sld_hub_inst|hub_tdo_reg~326 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.051 ns sld_hub:sld_hub_inst\|hub_tdo_reg 5 REG LCFF_X6_Y5_N29 2 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 6.051 ns; Loc. = LCFF_X6_Y5_N29; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~326 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.997 ns ( 33.00 % ) " "Info: Total cell delay = 1.997 ns ( 33.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.054 ns ( 67.00 % ) " "Info: Total interconnect delay = 4.054 ns ( 67.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.051 ns" { sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0] sld_hub:sld_hub_inst|hub_tdo_reg~323 sld_hub:sld_hub_inst|hub_tdo_reg~325 sld_hub:sld_hub_inst|hub_tdo_reg~326 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.051 ns" { sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0] {} sld_hub:sld_hub_inst|hub_tdo_reg~323 {} sld_hub:sld_hub_inst|hub_tdo_reg~325 {} sld_hub:sld_hub_inst|hub_tdo_reg~326 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 1.228ns 1.483ns 1.343ns 0.000ns } { 0.000ns 0.650ns 0.623ns 0.616ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.008 ns - Smallest " "Info: - Smallest clock skew is -0.008 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.304 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.304 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y7_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y7_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.813 ns) + CELL(0.000 ns) 3.813 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G1 198 " "Info: 2: + IC(3.813 ns) + CELL(0.000 ns) = 3.813 ns; Loc. = CLKCTRL_G1; Fanout = 198; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.813 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.825 ns) + CELL(0.666 ns) 5.304 ns sld_hub:sld_hub_inst\|hub_tdo_reg 3 REG LCFF_X6_Y5_N29 2 " "Info: 3: + IC(0.825 ns) + CELL(0.666 ns) = 5.304 ns; Loc. = LCFF_X6_Y5_N29; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.491 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.56 % ) " "Info: Total cell delay = 0.666 ns ( 12.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.638 ns ( 87.44 % ) " "Info: Total interconnect delay = 4.638 ns ( 87.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.304 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.304 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 3.813ns 0.825ns } { 0.000ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.312 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.312 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y7_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y7_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.813 ns) + CELL(0.000 ns) 3.813 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G1 198 " "Info: 2: + IC(3.813 ns) + CELL(0.000 ns) = 3.813 ns; Loc. = CLKCTRL_G1; Fanout = 198; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.813 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.666 ns) 5.312 ns sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_aoi:auto_generated\|dffe1a\[0\] 3 REG LCFF_X7_Y4_N5 1 " "Info: 3: + IC(0.833 ns) + CELL(0.666 ns) = 5.312 ns; Loc. = LCFF_X7_Y4_N5; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_aoi:auto_generated\|dffe1a\[0\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.499 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0] } "NODE_NAME" } } { "db/decode_aoi.tdf" "" { Text "C:/www_sdram/db/decode_aoi.tdf" 32 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.54 % ) " "Info: Total cell delay = 0.666 ns ( 12.54 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.646 ns ( 87.46 % ) " "Info: Total interconnect delay = 4.646 ns ( 87.46 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.312 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.312 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0] {} } { 0.000ns 3.813ns 0.833ns } { 0.000ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.304 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.304 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 3.813ns 0.825ns } { 0.000ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.312 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.312 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0] {} } { 0.000ns 3.813ns 0.833ns } { 0.000ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "db/decode_aoi.tdf" "" { Text "C:/www_sdram/db/decode_aoi.tdf" 32 8 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" { } { { "db/decode_aoi.tdf" "" { Text "C:/www_sdram/db/decode_aoi.tdf" 32 8 0 } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.051 ns" { sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0] sld_hub:sld_hub_inst|hub_tdo_reg~323 sld_hub:sld_hub_inst|hub_tdo_reg~325 sld_hub:sld_hub_inst|hub_tdo_reg~326 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.051 ns" { sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0] {} sld_hub:sld_hub_inst|hub_tdo_reg~323 {} sld_hub:sld_hub_inst|hub_tdo_reg~325 {} sld_hub:sld_hub_inst|hub_tdo_reg~326 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 1.228ns 1.483ns 1.343ns 0.000ns } { 0.000ns 0.650ns 0.623ns 0.616ns 0.108ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.304 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.304 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 3.813ns 0.825ns } { 0.000ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.312 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.312 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0] {} } { 0.000ns 3.813ns 0.833ns } { 0.000ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
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