test.fit.qmsg

Altera-jtag0

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:02 " "Info: Finished register packing: elapsed time is 00:00:02" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "68 I/O " "Extra Info: Packed 68 registers into blocks of type I/O" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "34 " "Extra Info: Created 34 register duplicates" {  } {  } 1 0 "Created %1!d! register duplicates" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Warning" "WCUT_PLL_NON_ZDB_COMP_CLK_FEEDING_IO" "pll:inst1\|altpll:altpll_component\|pll compensate_clock 0 " "Warning: PLL \"pll:inst1\|altpll:altpll_component\|pll\" is in normal or source synchronous mode with output clock \"compensate_clock\" set to clk\[0\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" {  } { { "altpll.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } } { "pll.v" "" { Text "C:/www_sdram/pll.v" 88 0 0 } } { "test.bdf" "" { Schematic "C:/www_sdram/test.bdf" { { -80 408 648 80 "inst1" "" } } } }  } 0 0 "PLL \"%1!s!\" is in normal or source synchronous mode with output clock \"%2!s!\" set to clk\[%3!d!\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" 0 0 "" 0}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "pll:inst1\|altpll:altpll_component\|pll clk\[0\] clk " "Warning: PLL \"pll:inst1\|altpll:altpll_component\|pll\" output port clk\[0\] feeds output pin \"clk\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } } { "pll.v" "" { Text "C:/www_sdram/pll.v" 88 0 0 } } { "test.bdf" "" { Schematic "C:/www_sdram/test.bdf" { { -80 408 648 80 "inst1" "" } } } } { "test.bdf" "" { Schematic "C:/www_sdram/test.bdf" { { -24 784 960 -8 "clk" "" } } } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Info: Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "16.274 ns register register " "Info: Estimated most critical path is register to register delay of 16.274 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns nios:inst\|cpu:the_cpu\|F_pc\[17\] 1 REG LAB_X26_Y6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X26_Y6; Fanout = 4; REG Node = 'nios:inst\|cpu:the_cpu\|F_pc\[17\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { nios:inst|cpu:the_cpu|F_pc[17] } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 4293 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.337 ns) + CELL(0.370 ns) 2.707 ns nios:inst\|onchip_mem_s1_arbitrator:the_onchip_mem_s1\|cpu_instruction_master_requests_onchip_mem_s1~319 2 COMB LAB_X17_Y9 2 " "Info: 2: + IC(2.337 ns) + CELL(0.370 ns) = 2.707 ns; Loc. = LAB_X17_Y9; Fanout = 2; COMB Node = 'nios:inst\|onchip_mem_s1_arbitrator:the_onchip_mem_s1\|cpu_instruction_master_requests_onchip_mem_s1~319'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.707 ns" { nios:inst|cpu:the_cpu|F_pc[17] nios:inst|onchip_mem_s1_arbitrator:the_onchip_mem_s1|cpu_instruction_master_requests_onchip_mem_s1~319 } "NODE_NAME" } } { "nios.v" "" { Text "C:/www_sdram/nios.v" 1303 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.548 ns) + CELL(0.370 ns) 4.625 ns nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_instruction_master_requests_cpu_jtag_debug_module~249 3 COMB LAB_X21_Y5 23 " "Info: 3: + IC(1.548 ns) + CELL(0.370 ns) = 4.625 ns; Loc. = LAB_X21_Y5; Fanout = 23; COMB Node = 'nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_instruction_master_requests_cpu_jtag_debug_module~249'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.918 ns" { nios:inst|onchip_mem_s1_arbitrator:the_onchip_mem_s1|cpu_instruction_master_requests_onchip_mem_s1~319 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~249 } "NODE_NAME" } } { "nios.v" "" { Text "C:/www_sdram/nios.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.166 ns) + CELL(0.370 ns) 6.161 ns nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_address\[8\]~125 4 COMB LAB_X20_Y7 8 " "Info: 4: + IC(1.166 ns) + CELL(0.370 ns) = 6.161 ns; Loc. = LAB_X20_Y7; Fanout = 8; COMB Node = 'nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_address\[8\]~125'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.536 ns" { nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~249 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[8]~125 } "NODE_NAME" } } { "nios.v" "" { Text "C:/www_sdram/nios.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.703 ns) + CELL(0.206 ns) 8.070 ns nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_address\[6\]~129 5 COMB LAB_X18_Y3 33 " "Info: 5: + IC(1.703 ns) + CELL(0.206 ns) = 8.070 ns; Loc. = LAB_X18_Y3; Fanout = 33; COMB Node = 'nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_address\[6\]~129'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.909 ns" { nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[8]~125 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[6]~129 } "NODE_NAME" } } { "nios.v" "" { Text "C:/www_sdram/nios.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.330 ns) + CELL(0.202 ns) 9.602 ns nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|Equal0~67 6 COMB LAB_X18_Y5 4 " "Info: 6: + IC(1.330 ns) + CELL(0.202 ns) = 9.602 ns; Loc. = LAB_X18_Y5; Fanout = 4; COMB Node = 'nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|Equal0~67'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.532 ns" { nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[6]~129 nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~67 } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 508 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.617 ns) + CELL(0.650 ns) 11.869 ns nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1937 7 COMB LAB_X13_Y7 1 " "Info: 7: + IC(1.617 ns) + CELL(0.650 ns) = 11.869 ns; Loc. = LAB_X13_Y7; Fanout = 1; COMB Node = 'nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1937'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.267 ns" { nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~67 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1937 } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 3884 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.580 ns) + CELL(0.370 ns) 13.819 ns nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1938 8 COMB LAB_X17_Y4 1 " "Info: 8: + IC(1.580 ns) + CELL(0.370 ns) = 13.819 ns; Loc. = LAB_X17_Y4; Fanout = 1; COMB Node = 'nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1938'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.950 ns" { nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1937 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1938 } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 3884 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.330 ns) + CELL(0.206 ns) 15.355 ns nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1939 9 COMB LAB_X17_Y6 1 " "Info: 9: + IC(1.330 ns) + CELL(0.206 ns) = 15.355 ns; Loc. = LAB_X17_Y6; Fanout = 1; COMB Node = 'nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1939'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.536 ns" { nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1938 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1939 } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 3884 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.206 ns) 16.166 ns nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1940 10 COMB LAB_X17_Y6 1 " "Info: 10: + IC(0.605 ns) + CELL(0.206 ns) = 16.166 ns; Loc. = LAB_X17_Y6; Fanout = 1; COMB Node = 'nios:inst\|cpu:the_cpu\|av_ld_byte0_data_nxt\[2\]~1940'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1939 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1940 } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 3884 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 16.274 ns nios:inst\|cpu:the_cpu\|av_ld_byte0_data\[2\] 11 REG LAB_X17_Y6 1 " "Info: 11: + IC(0.000 ns) + CELL(0.108 ns) = 16.274 ns; Loc. = LAB_X17_Y6; Fanout = 1; REG Node = 'nios:inst\|cpu:the_cpu\|av_ld_byte0_data\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1940 nios:inst|cpu:the_cpu|av_ld_byte0_data[2] } "NODE_NAME" } } { "cpu.v" "" { Text "C:/www_sdram/cpu.v" 4708 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.058 ns ( 18.79 % ) " "Info: Total cell delay = 3.058 ns ( 18.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.216 ns ( 81.21 % ) " "Info: Total interconnect delay = 13.216 ns ( 81.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.274 ns" { nios:inst|cpu:the_cpu|F_pc[17] nios:inst|onchip_mem_s1_arbitrator:the_onchip_mem_s1|cpu_instruction_master_requests_onchip_mem_s1~319 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~249 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[8]~125 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[6]~129 nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~67 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1937 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1938 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1939 nios:inst|cpu:the_cpu|av_ld_byte0_data_nxt[2]~1940 nios:inst|cpu:the_cpu|av_ld_byte0_data[2] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}